We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8411

PROM XC18V00 - What are the program options for an 1800 in the JTAG Programmer?


Keywords: XC18V00, 1800, parallel, load FPGA, skip user array

Urgency: Standard

General Description:
What are the program options for an 1800 in the JTAG Programmer?


Erase Before Programming: All 18V00s should be erased before programming. For your convenience this is checked by default.

Verify: Read back the MCS/EXO file stored in the 1800 and compare it to the MCS/EXO file associated with it in the JTAG Programmer.

Parallel Mode: When checked, this will set a bit in the 1800 to allow the data to be output on D0-D7 in parallel. When unchecked, this will set the 1800 for serial output mode (D0).

Load FPGA: After the program operation completes, the 1800 will pulse the CF/ pin low to initiate FPGA reconfiguration. For more details on the CF/ pin, please see (Xilinx Answer 7472).

Read Protect: Sets a security bit to prevent JTAG Programmer from being able to read back the MCS/EXO file.

Skip User Array: Do not program the MCS/EXO into an 1800. This option allows you to program the parallel or read protect bit without having to re-program the entire device.

NOTE: If you select "Skip User Array" and leave "Parallel" and/or "Read Protect" unchecked, these bits will NOT be unset. To do this, you must reprogram the entire array.
AR# 8411
Date Created 09/01/2007
Last Updated 05/06/2003
Status Archive