UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8427

3.1i JTAG Programmer - Error: "<design_name>(Device1): Programming terminated due to errors"

Description

Keywords: JTAG, terminated, programmer, download, due to, errors, Virtex, done

Urgency: Standard

General Description:
When I use JTAG programmer to download a bit file onto a Virtex device, the following error message is reported:

"<design_name>(Device1): Reading bit-stream file...done."
"<design_name>(Device1): Programming device...done."
"<design_name>(Device1): Programming terminated due to errors."

Solution

1

After the JTAG Programmer finishes configuration (indicated by the DONE pin going high), it performs a read on the status register. This is a redundant check to determine whether or not DONE is high. If the BitGen option "disable Readback" is selected, the part is prevented from relaying this information to the software. Thus, the following error may occur after configuration:

"<design_name>(Device1)": Programming terminated due to errors.

This error can be ignored because it is a redundant check by software. If the DONE pin is physically probed, you will see that the part was configured successfully. (This error message has been seen when Virtex devices are targeted.)

For 3.1i JTAG Programmer errors related to this topic, please see (Xilinx Answer 8427).

2

The configuration is successful; the JTAG Programmer message is misleading and may be ignored.

Details regarding the misleading error message are as follows:

The "Program" operation in JTAG Programmer invokes the following sequence of operations:

1. An instruction register "integrity check".
2. An IDCODE check on the devices.
3. Devices are put in BYPASS or HIGHZ mode.
4. The "active" Virtex is put into JTAG configuration mode.
5. The bit stream is downloaded to configure the "active" Virtex.
6. The state of the DONE signal is checked.
7. Devices are returned to BYPASS mode.

If JTAG Programmer completes the bit stream download without error, the "programming done" message is reported. JTAG Programmer then immediately checks the DONE signal to verify that the device started successfully with the new configuration. If the DONE signal is still low (i.e., the Virtex has not "started"), JTAG Programmer will issue the "terminated with errors" message.

The DONE signal may remain low for two reasons:

1. The configuration failed.
2. Another device is holding DONE low to delay the startup sequence.

The JTAG Programmer will report the misleading error message if the DONE pin on the FPGA is forced to stay low by an external source of control. This can be the result of the DONE pins being tied together to hold off the startup sequence until all devices have configured successfully.

Configuration of one device will result in the misleading error message if another device is still blank and is holding the common DONE signal low.

Other possible reasons that this message is reported are:

1. The JTAG clock was not selected as the startup clock.
2. A DLL is not synchronizing.
AR# 8427
Date Created 08/31/2007
Last Updated 09/30/2005
Status Archive
Type ??????