UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8483

Virtex - VHDL code for SelectLink application

Description

Keywords: Virtex, SelectLink, Select, Link, VHDL, Verilog

Urgency: Standard

General Description:
A Verilog code for SelectLink applications for Virtex devices is available at: http://www.xilinx.com/applications/slcv/selectlink.htm

(Currently, Xilinx does not plan to add a VHDL code generator.)

Solution

1

Most synthesis/simulation tools can translate both Verilog and VHDL.
A workaround is to instantiate the generated Verilog macro in your VHDL design.

2

If your synthesis/simulation tool can't translate VHDL and Verilog you have to
translate the Verilog code into VHDL.
AR# 8483
Date Created 01/24/2000
Last Updated 04/25/2006
Status Archive
Type General Article