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AR# 8791

2.1i COREGEN, C_IP4: Single Port Block Memory does not support negative edge / falling edge clock


Keywords: Coregen, falling, edge, block, memory, falling_edge, rising

Urgency: Standard

General Description:
The last page of the CORE Generator datasheet for the Single Port Block
Memory lists a number of XCO file parameters that can be used to
customize the core, including the "Clock_On" parameter, which gives you
the option of specifying a rising or falling edge clock. This feature is actually
not supported in the module GUI.


This capability has been added to the C_IP5 version of the GUI, but
because of a bug with this functionality, please refer to the
workaround described in (Xilinx Answer #9559).
AR# 8791
Date Created 03/09/2000
Last Updated 09/03/2001
Status Archive
Type General Article