UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8792

** OBSOLETE ** 3.1i Timing Simulation - Warning: "*/X_SUH SETUP Low VIOLATION ON I WITH RESPECT TO CLK"

Description

Keywords: Timing, Simulation, ngdanno, X_SUH, GSUH, setup, hold, violation, negative, falling, edge

Urgency: Standard

General Description:

During a Timing Simulation, the following error occurs:
# ** Warning: */X_SUH SETUP Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.01 ns; Observed := 0 ns; At : 400 ns
# Time: 400 ns Iteration: 0 Instance: /test_top/gsuh_sig1_in_clk

At 400 ns the clock edge is falling. All FFs are positive edge triggered. Why is this violation occuring?

Solution

This is a discontinuity between the SDF writer and the VHDL SimPrim model for the X_SUH component. The SDF writer will properly annotate the relevant data for X_SUH, as in the above example data with respect to the positive edge of CLK.

The problem arises because the SDF writer does not write data for all other timing checks that are in the simprim_VITAL file, such as data with respect to a negative edge CLK. By default, the simprims_VITAL.vhd has 0.01ns (or non-zero) values for timing checks; when simulation is run, this flags setup violations even though the check is invalid.

The work-around is to change the timing checks in the simprims_Vcomponents.vhd file (lines 4319 to 4772) to 0.0ns, then recompile this file. The SDF will then properly annotate real values.

This problem has been fixed in the 4.1i release.
AR# 8792
Date Created 08/31/2007
Last Updated 07/09/2002
Status Archive
Type ??????