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# AR# 8836

## Description

General Description:

How do I implement a latch using ABEL, VERILOG, or VHDL?

## Solution

The following code shows how to create registered and combinatorial latches using ABEL:

// Registered Latch

MODULE top

data0 pin;

latch_enable pin;

out0 pin istype 'reg';

Equations

out0 := data0;

out0.lh = latch_enable;

END top

// Combinatorial Latch

MODULE latch

data pin;

latch pin;

dout pin istype 'retain';

// dout_temp node istype 'retain';

Equations

dout = data & latch # dout & !latch

# dout & data; // redundant product term

// dout_temp = data & latch # data & dout;

// dout = dout_temp # data & !latch; // redundant pterm

END

There are two forms of a combinational latch given; the commented lines are necessary for the alternate form. The commented version may be useful for situations where the data equation is large. Because of the "retain" attribute, when the data equation is large, the software will not be able to appropriately minimize the logic, which results in high Product Term usage.

The following code shows how to create registered latches using VHDL:

library IEEE;

use IEEE.std_logic_1164.all;

entity top is

port (

gate: in STD_LOGIC;

din: in STD_LOGIC;

dout: out STD_LOGIC

);

end top;

architecture top_arch of top is

begin

process (GATE, DIN)

begin

if GATE='1' then

DOUT <= DIN;

end if;

end process;

end top_arch;

The following code shows how to create registered latches using Verilog:

module top (DIN, GATE, DOUT) ;

input DIN ;

input GATE ;

output DOUT ;

reg DOUT ;

always @ (GATE or DIN)

begin

if(GATE)

DOUT =DIN;

end

endmodule

AR# 8836
Date 12/15/2012
Status Active
Type General Article