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AR# 8909

9.1i Virtex PAR - "Warning:Place:1697 - Design constraints indicate that low-skew routing resources should be used for signal "net_name"..."

Description

The Virtex and Spartan-II families have low-skew routing resources available for high-fanout nets. It is possible to access these low-skew lines directly by placing the following constraint in the UCF: 

 

NET "net_name" USELOWSKEWLINES; 

 

However, when these low-skew lines are used, the following warning is reported during PAR: 

 

"Warning:Place:1697 - Design constraints indicate that low-skew routing resources should be used for signal "net_name". Range or LOC constraints have been applied to some or all of the signal leads. To help minimize skew, Xilinx recommends that the LOC or range constraints be applied to minimize the number of CLB columns spanned by loads of this signal." 

 

What should I do to minimize the skew?

Solution

There are specific access points for the secondary or low-skew routing. In order to minimize skew and delay, it is recommended that you place the net that will be connected to the low-skew routing as close to the access points as possible. This will minimize the routing required on local routing.  

 

The access points for the secondary routing are near the global clock pads. Therefore, try to LOC the nets you wish to be placed on secondary routing as close to the top or bottom center of the die as possible. For more information on constraining designs, please refer to the (Xilinx XAPP400): "Constraining Virtex Design in 2.1i".

AR# 8909
Date Created 08/21/2007
Last Updated 05/14/2014
Status Archive
Type General Article