A design is done using the differential inputs (LVPECL or LVDS). However, when I view the implemented files, the N-side input does not exist (pad report, FPGA Editor, Floorplanner, etc).
When using differential signaling (LVDS or LVPECL), only the P-side of the signal is analyzed by the Xilinx tools. If the tools see that the P-side is configured, the Placer and BitGen will automatically account for this and correctly configure the device.
However, the N-side IOB cannot be viewed in tools such as FPGA Editor.