UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 8964

Virtex Configuration - Setting the DLL wait cycle

Description

General Description: What should a user look for when setting the startup sequence to wait for DLL lock?

Solution

Two things must be done to make sure the device waits for the DLL's to lock:

1) Put the STARTUP_WAIT = TRUE property in the UCF file or in the code for each appropriate DLL.

2) Set the Lck_cycle to something other than NoWait. This can be done in the configuration templates if you are using the GUI (either Foundation or Design Manager) or with -g Lck_cycle:chosencycle if command line is used.

The lck_cycle can be set to a startup phase before DONE, GWE, GTS, or GSR are triggered if there is no board-level deskew happening. GTS controls the global tri-state, which will disable all outputs. Inputs are valid, but if outputs are required for the DLL to lock, the device will never configure in this situation. If that is a problem, set lck_cycle to a phase after GTS is de-asserted.

AR# 8964
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article