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AR# 9067

3.1i Foundation ISE: View VHDL Test Bench Template incorrectly converts integer type to std_logic_vector type


Keywords: VHDL, Test Bench Template, convert, integer, std_logic_vector

Urgency: Standard

General Description:
When a VHDL source has been selected, one of the processes associated
with this source is, "View VHDL Test Bench Template". This process creates
a Test Bench Template specific to the selected source file. If the source file
contains ports of type integer, they will be incorrectly represented in the Test
Bench generated.

For example, if the source file contains the following:

entity top is
port ( a : out integer range 0 to 15;
clk : in std_logic);
end top;

The Test Bench will contain the following component instantiation:

component test
port( clk : in std_logic;
a : out std_logic_vector(0 to 15));
end component;

VHDL Test Bench Template range is converting integer to std_logic_vector.


There are two solutions:

1- Hand edit the Test Bench Template to include the correct port types.

2- Change the source file.
AR# 9067
Date Created 08/31/2007
Last Updated 01/01/2003
Status Archive
Type General Article