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AR# 9071

3.x FPGA Express - FPGA Express does not place IOB=TRUE constraints FFs in a 3-state condition


Keywords: FPGA Express, Verilog, VHDL, 3.3, 3.4, IOB, TRUE, constraint, Register

Urgency: Standard

General Description:
FPGA Express does not place an IOB=TRUE constraint in the netlist on flip-flops that are in a 3-state condition, even though the "Use I/O Reg" option is enabled in the FPGA Express constraints editor.


This is a known issue, and it will be fixed in a future software release.

Meanwhile, you may work around the problem by using the "-pr b" option in MAP. This option instructs MAP to pack registers into the IOBs whenever possible.

- From the Design Manager, select Design -> Options -> Edit Implementation Options.

- In the "Optimize and Map" tab, set "Pack I/O Registers/Latches into IOBs to:" to be "Inputs and Outputs." This will turn on the "-pr b" switch.
AR# 9071
Date Created 04/17/2000
Last Updated 08/11/2003
Status Archive
Type General Article