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AR# 9097

Virtex-II/-II Pro, BUFGMUX - What is the setup time for the select or enable signal of BUFGCE/BUFGMUX?

Description

Keywords: I0, I1, Tgsi0, Tgsi1, I/O

What is the setup time for the select pin (S) of BUFGMUX or the enable (CE) pin of BUFGCE?

The referenced data sheets below include the following statement in the BUFGCE section:
"CE must not change during a short setup window just prior to the rising clock edge on the BUFGCE input I. Violating this setup time requirement can result in an undefined runt pulse output."

The referenced data sheets below include the following statement in the BUFGMUX section :
"The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup time prior to the rising edge of the presently selected clock; that is, prior to the rising edge of the BUFGMUX output O. Violating this setup time requirement can result in an undefined runt pulse output."

Virtex-II
http://www.xilinx.com/support/documentation/data_sheets/ds031.pdf
Go to Module Descriptions -> Detailed Functional Description

Virtex-II Pro
http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf
Go to Module Descriptions -> Functional Description

Solution

The setup time of the Select pin (S) or the Enable pin (CE) is reported by the Timing Analyzer or TRCE as Tgsi0 and Tgsi1. This value is reported as part of the data vs. clock path analysis (e.g., when an "OFFSET IN" constraint is applied).

Tgsi0 report for Virtex-II Pro speed grade -7
Tgsi0 report for Virtex-II Pro speed grade -7


AR# 9097
Date Created 08/21/2007
Last Updated 10/09/2008
Status Active
Type General Article