UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9132

3.1i MAP: Inputs incorrectly initialized to 1 instead of 0 in backannotated timing simulation

Description

Keywords: simulation, init, initialize, accumulator, adder, subtractor, subtracter, register

Urgency: hot

General Description:
I0 pins driven by GND in a Virtex design may initialize incorrectly to
1 instead of 0.

This may be due to a problem in the 3.1i Mapper which results in an incorrect
NGM file. When the NGM file is subsequently read in as an input to NGDANNO
during the process of generating a backannotated timing simulation netlist, the resulting
simulation netlist may contain instances where inputs that are supposed to be
driven by 0 are driven by a 1 instead.

The problem is associated with an Virtex or Virtex-II LUT that is configured as a buffer,
with the least significant LUT input pin, I0, driven by GND. The GND connection may
have been specified by the user, or it may be preconfigured in a CORE Generator core's
EDIF netlist in response to some user-specified INIT value.

The problem has been observed in the Virtex Accumulator, Adder/Subtracter,
and FD-based Register).

Solution

The workaround is to omit the NGM file when running NGDANNO to work around this bug.

If you are processing the design through Design Manager, de-select the switch for "Correlate
Simulation Data to Inpur Design".


AR# 9132
Date Created 04/24/2000
Last Updated 12/07/2004
Status Archive
Type General Article