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AR# 9155

Virtex Configuration - Configuration fails due to power supply sequencing


General Description:

Configuration in a master-serial mode fails repeatedly when the board is brought up for the first time. DONE does not go High, INIT never goes Low, and the CCLK continues to run.

This seems to indicate that an error has not occurred, but the configuration does not complete successfully. Additionally, I see this same type of failure when I bring up the core voltage (VCCINT) and the I/O voltages (VCCIO) at different times.

In all cases, if I simply toggle the program pin (PROG), the device re-programs and configuration completes successfully. Is this a power-sequencing issue?


This is most likely not a problem with the Virtex/-E device, but is rather a problem with the reset time necessary for the PROM to correctly complete its power-on-reset routine. Virtex architectures are very quick to start -- more so than any other Xilinx family, including the Xilinx PROMs. If the PROM does not have enough time to clear its internal registers so that it begins at location "0" (instead of at another location), the Virtex device never processes the SYNC word, and it cannot configure. To determine whether or not this is the case, look at the CCLK frequency on a scope. If Virtex did not get the SYNC word and the subsequent CCLK bump, the frequency will be ~2 MHz; if it did, then the frequency should be 4 MHz (or whatever frequency was used to set "bitgen -g" configrate:#). For further information about the SYNC word, see (Xilinx Answer 7891).

Once the power supplies are at their operating values, and the board is reset through the PROG pin, the device will successfully configure (since the power-on-reset operation has already completed).

Another possible way to work around this is to increase the INIT/OE resistor to ~10 KOhm and add a 10 uF cap to INIT/OE to GND. This increases the INIT rise time, which gives the PROM enough time to complete its power-on reset cycle.

NOTE: This is not the case with Xilinx Platform Flash PROMs, XC18V00 PROMs, or XC17V00 PROMs. These families hold themselves in a reset state until the power-on-reset sequence has finished successfully.

It is also possible that the PROM did not go below its POR (Power On Reset) trip point when the board was un-powered or power cycled. For more information, see (Xilinx Answer 14444).

AR# 9155
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article