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AR# 9174

Virtex-E - How do I use LVDS, LVPECL macros (such as IBUFDS_FD_LVDS, OBUFDS_FD_LVDS) in designs?

Description

The Xilinx Application Note (Xilinx XAPP133): "Using the Virtex SelectI/O Resource" contains instructions on instantiating LVDS and LVPECL-related components such as IBUFDS_FD_LVDS, IBUFDS_FDP_LVDS, and OBUFDS_FD_LVDS. However, if these macro netlists are not present in the design directory, the following errors are reported in NGDBuild:

"ERROR:NgdHelpers:312 - logical block "U6" of type "OBUFDS_FD_LVDS" is unexpanded."

How do I avoid this error and use these components properly?

Solution

As these LVDS and LVPECL-related components are macros, the respective EDIF netlists must be present in the design directory before implementation.

The LVDS and LVPECL-related files can be downloaded at:

PC:

http://www.xilinx.com/txpatches/pub/applications/xapp/io_lvds.zip

Workstation:

http://www.xilinx.com/txpatches/pub/applications/xapp/io_lvds.tar.gz.

The following VHDL code illustrates the instantiation of OBUFDS_FD_LVDS:

library ieee;

use ieee.std_logic_1164.all;

entity lvds_test is

port (

CLKP: in STD_LOGIC;

CLKN: in STD_LOGIC;

DP: in STD_LOGIC;

DN: in STD_LOGIC;

QP: out STD_LOGIC;

QN: out STD_LOGIC

);

end lvds_test;

architecture lvds_arch of lvds_test is

signal CLKPOUT, IFD_O, CLK_buf : STD_LOGIC;

component IBUFG_LVDS

port (I: in std_logic; O: out std_logic);

end component;

component BUFG

port (I: in std_logic; O: out std_logic);

end component;

component IBUFDS_FD_LVDS -- lvds_macros

port ( I, IB, C : in std_logic; Q : out std_logic );

end component;

component OBUFDS_FD_LVDS

port (

D, C : in std_logic;

O, OB : out std_logic

);

end component;

begin

U1: IBUFG_LVDS port map( I=>CLKP, O=>CLKPOUT );

U2: IBUFG_LVDS port map( I=>CLKN, O=>open );

U3: BUFG port map(I => CLKPOUT, O => CLK_buf);

U4: ibufds_fd_lvds port map ( I =>DP, IB => DN, C => CLK_buf, Q => IFD_O );

U5: obufds_fd_lvds port map ( D => IFD_O, C => CLK_buf, O => QP, OB => QN );

end lvds_arch;

In version 4.x of the Xilinx tools, you must manually prohibit the use of N-side of the differential buffer. You can prohibit the use of the N-side pin using the following syntax in the UCF file:

CONFIG PROHIBIT=XX;

AR# 9174
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article