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AR# 9177

Virtex/Virtex-E - Can I use Global Clock Input pins as general I/Os?

Description

Keywords: Virtex, Global, Clock, I/O, IO, input

Urgency: Standard

General Description:
Can I use the Global Clock pins as general I/Os in Virtex/Virtex-E?

Solution

1

In addition to using Global Clock pins as clock inputs, you may also use them as general inputs only. (They cannot be used as outputs.)

To use them as inputs, perform these steps:

1. Instantiate an IBUFG in your circuit, and place the input signal (that is to be placed on the Global pin) on the input of the IBUFG.

2. Connect the output of the IBUFG to the rest of your circuit as you normally would.

2

1. Instantiate an BUFGP in your circuit, and place the input signal (that is to be placed on the Global pin)
on the input of the BUFGP.

2. Connect the output of the BUFGP to the rest of your circuit as you normally would.

The reason for that is the tool would instantiate automatically a normal IO buffer if you not instantiate one. However
in the Clock-pin there is no such component. Then the map tool would complain about a error.
BUFGP is a Clock-IO buffer.

You instantiate it by using the language template:

component BUFGP
port (I: in std_logic; O: out std_logic);
end component;
signal a: std_logic;

begin

usro<=not CLK_SIG;
usro<=usri;

U1: BUFGP port map (I => usri, O => a);

AR# 9177
Date Created 04/28/2000
Last Updated 09/22/2003
Status Archive
Type General Article