UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9178

SYNPLIFY: How to merge flip-flops to IOB in Virtex/Virtex-E/Spartan-II devices? (VHDL/Verilog)

Description

Keywords: register, virtexe, iob=true, xc_props, xc_ioff

Urgency: Standard

General Description:
How do I merge registers to IOB in Virtex/Virtex-E/Spartan-II devices? Synplify 5.3.1 does not merge registers to IOB by default. However, customers can pass xc_props IOB=TRUE attribute to do this. See the example below.

NOTE: Tested in 5.3.1.

Solution

1

//Verilog example with IOB=TRUE on an instantiated flip-flop.
// This example shows how to use OE FF.

`include "virtex.v"

module iobtrue (O, C, D, E)
/* synthesis black_box_pad_pin="O" */;
input C, D, E;
output O;

wire O_OUT;

FDCE U0 (.D (D), .CE (1'b1), .C (C), .CLR (1'b0), .Q (O_OUT)) /* synthesis xc_props = "IOB=TRUE" */;
OBUFT U1 (.I (O_OUT), .T (~E), .O (O));
endmodule

2

-- VHDL example with IOB=TRUE on inferred flip-flops.

library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;

entity d_register is
port (CLK : in STD_LOGIC;
D_IN : in STD_LOGIC_VECTOR(3 downto 0);
Q_OUT : out STD_LOGIC_VECTOR(3 downto 0));
attribute xc_props of Q_OUT : signal is "IOB=TRUE";
end d_register;

architecture XILINX of d_register is

begin

process (CLK)
begin
if rising_edge(CLK) then
Q_OUT <= D_IN;
end if;
end process;

end XILINX;

3

-- VHDL example with IOB=TRUE on an instantiated flip-flop.
-- This example show how to use OE FF

library IEEE, Synplify, unisim;
use IEEE.std_logic_1164.all;
use Synplify.attributes.all;
use unisim.vcomponents.all;

entity iobtrue is port (
D: in std_logic;
C: in std_logic;
E: in std_logic;
O: out std_logic);
attribute black_box_pad_pin of iobtrue: entity is "O";
end iobtrue;

architecture Xilinx of iobtrue is
signal O_OUT : std_logic;

attribute xc_props of U0: label is "IOB=TRUE";

begin

U0:FDCE port map (D =>D, CE => '1', C => C, CLR => '0', Q => O_OUT);
U1:OBUFT port map (I => O_OUT, T => not E, O => O);
end xilinx;

4

// Verilog exampe with IOB=TRUE on inferred flip-flops
module dff(clk, rst, d, q);
input [3:0] d;
input clk, rst;
output [3:0] q;
reg [3:0] q /* synthesis xc_props = "IOB=true" */;

always @ (posedge clk)
begin
if (rst)
q = 4'b0000;
else
q = d;
end

endmodule
AR# 9178
Date Created 08/21/2007
Last Updated 09/16/2003
Status Active
Type General Article