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AR# 9215

3.1i Virtex-E, CLKDLL - ClLKDLL doesn't lock in simulation if clock remains low for one period upon start of simulation.

Description

Keywords: Virtex-E, CLKDLL, MTI, simulation, lock, low, clock, period, clock, cycle

Urgency: Standard

General Description:
If the clock stays low for one clock cycle at the start of simulation, the CLKDLL
fails to lock. For example, the CLKDLL will not lock in the following case:

always
begin
clk_in = 1'b0; #40.000 ;
forever
begin
clk_in = 1'b1; #20.000 ;
clk_in = 1'b0; #20.000 ;
end
end

However, if the clock starts running at the start of simulation, the CLKDLL
locks as it should, as in the example below:

always
begin
clk_in = 1'b0; #39.000 ; //also; 41.000 or anything other than 40.000!!
forever
begin
clk_in = 1'b1; #20.000 ;
clk_in = 1'b0; #20.000 ;
end
end

This problem only occurs if the clock is kept low for exactly one clock cycle
at the start of simulation.

Solution

This problem is fixed in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates. The first
service pack containing the fix is 3.1i Service Pack 6.
AR# 9215
Date Created 08/31/2007
Last Updated 08/25/2003
Status Archive
Type ??????