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AR# 9297

4.1i Timing - A Multi-Cycle (FROM:TO) path constraint is picked up by a PERIOD constraint (Intersection problem)

Description

Urgency: Hot

General Description:

The following time specs are defined to create multi-cycle paths. These constraints should include all flip-flops to a particular timing group (GroupA and GroupB); however, some of the registers are placed into the PERIOD time spec, causing long run times and invalid paths.

The following are examples of the PERIOD and the FROM:TO constraints:

NET clock TNM_NET = clock grp;

TIMESPEC TS_CLK = PERIOD clock_grp 20;

TIMESPEC "TS_grpA" = FROM "FFS" TO "GroupA" TS_CLK" * 2;

TIMESPEC "TS_grpB" = FROM "FFS" TO "GroupB" "TS_CLK" * 2;

For more information, please also see (Xilinx Answer 5939) and (Xilinx Answer 5965).

Solution

This issue occurs when a specific FROM:TO (multi-cycle) constraint is not a subset (or smaller portion) of the overall (PERIOD) constraint. Because the multi-cycle constraint is not a subset of the Period constraint, the tools cannot remove the paths covered by the multi-cycle constraint. The correct subset of the PERIOD is illustrated in Figure 1.

Figure 1 - Correct Subset of FFs with respect to PERIOD
Figure 1 - Correct Subset of FFs with respect to PERIOD


The figure shows that the PERIOD spec defines many paths, and that TW_SLOW defines a subset of paths in PERIOD spec. The result is that TW_SLOW paths are removed from PERIOD coverage.

In Figure 2, the G is a superset time spec (e.g., PERIOD spec), the H is a subset time spec (e.g., MAXDELAY or TIG spec), and G' is the result when H is removed from G; this means that H must be a subset of G.

Figure 2 - Correct Subset/Super-set Relationship
Figure 2 - Correct Subset/Super-set Relationship


Another issue involves the intersection of these time groups with other time groups. If more than one multi-cycle constraint covers the same path or time group that is covering the same source or destination, this is called an "intersection". The tools do not know in which time group or multi-cycle constraint to keep the path, and from which group to remove it. An example of intersection is illustrated in Figure 3. The examples in Figure 4 and Figure 5 also illustrate the interaction between two time groups and the PERIOD.

Figure 3 - Intersection between TS_SLOW and the PERIOD
Figure 3 - Intersection between TS_SLOW and the PERIOD


Figure 4 - Interaction between TS_SLOW1, TS_SLOW2, and the PERIOD
Figure 4 - Interaction between TS_SLOW1, TS_SLOW2, and the PERIOD


Figure 5 - Interaction between TS_SLOW, TS_SLOWER, and the PERIOD
Figure 5 - Interaction between TS_SLOW, TS_SLOWER, and the PERIOD


In most cases, simply modifying the time groups to remove unnecessary overlap will solve this issue. Please see the other solutions in this answer for possible work-arounds.

The interaction issue is fixed in the latest 3.1i Service Pack, available at:

http://support.xilinx.com/support/techsup/sw_updates.

The first service pack containing the fix is 3.1i Service Pack 3.

(The intersection and subset issues are still under investigation.)

The primary time group defined by the PERIOD time spec includes the registers that are also defined in the "GroupA" and "GroupB" time groups. The constraints to "GroupA" and "GroupB" are MAXDELAYs from the FFs. You may simply remove the "GroupA" and "GroupB" registers from the PERIOD spec time group using an EXCEPT; if you then apply the period to the result, the analysis should work properly.

For example:

NET clock TNM_NET = clock_grp;

TIMEGRP slow_end = clock_grp EXCEPT GroupA GroupB;

TIMESPEC TS_slow_end = PERIOD slow_end 30;

TIMESPEC "TS_grpA" = FROM "FFS" TO "GroupA" TS_slow_end" * 2;

TIMESPEC "TS_grpB" = FROM "FFS" TO "GroupB" "TS_slow_end" * 2;

You may create the original time groups in Constraints Editor as described in Resolution 3. The creation of a new time group from an existing time group must be performed manually in the User Constraints File (UCF). The keyword "EXCEPT" must also be manually placed into the UCF.

If the clock signal is driving a DLL, the TNM_NET constraint must be placed on an output signal of the DLL.. This should also be placed manually into the UCF.

You may also work around this issue by consolidating the slow exception specifications.

- First, group the flip-flops and the other slow source time groups into a larger source time group.

- Then, group the two smaller destination time groups into a larger target time group.

- Finally, replace the slow exception (FROM:TOs) time constraints with one new time spec (FROM large_sources TO large_targets). This solves the issue and extracts the paths from the PERIOD time spec.

For example (if you perform this process manually):

TIMEGRP large_source = small_src_group1 small_src_group2;

TIMEGRP large_target = small_dest_group1 small_dest_group2;

TIMESPEC TS01 = FROM large_source TO large_target 30;

You may create the large_source and large_target time groups in Constraints Editor. Launch Constraints Editor and open or create the User Constraints File (UCF).

- Select the Advanced tab, press the Create button, and select "Group Elements Associated by Nets (TNM_NET)".

- Enter the time group name in the "Time Name" text box and select the desired "Design Element Type" (such as "Enable Nets").

- Select the specific enable nets for the multi-cycle group and press the Add button to include them in the group.

- Press "Apply" or "OK" to write out the time group.

Alternatively, you may select "Create" and choose "Group by Instance Name (TNM)" from the Advanced tab.

- Enter the time group name in the "Time Name" text box and select the desired "Design Element Type" (such as FFs or RAMs).

- Select the specific elements or items for the group and press the Add button to include them in the group.

- Select the next "Design Element Type", select the elements, and add them. Repeat until all elements have been added to create the larger time groups.

- Press the "Apply" or "OK" button to write out the time group.

The following Constraints Editor example illustrates the creation of time groups:

INST counter_reg<11> TNM = large_source;

INST counter_reg<22> TNM = large_source;

INST ram_bob<12> TNM = large_source;

INST ram_bob<53> TNM = large_source;

INST xcounter_reg<52> TNM = large_target;

INST xcounter_reg<24> TNM = large_target;

INST nail_ram<13> TNM = large_target;

INST nail_ram<26> TNM = large_target;

TIMESPEC TS01 = FROM large_source TO large_target 30;

The remaining intersection issue was fixed in the 5.1i software release.

AR# 9297
Date Created 08/31/2007
Last Updated 01/18/2010
Status Archive
Type General Article