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AR# 9332

3.1i CORE Generator - Known Issues in the D_IP1 IP Update.

Description

Keywords: D_IP1, COREGen, DA, FIR, filter, sine, cosine, LUT, lookup, table, Virtex, adder, subtracter, subtractor, FD, based, shift, register, accumulator, Virtex-II, Block, RAM, memory, problem, single port, dual port, block memory, Asynchronous FIFO, Release Notes, distributor memory, FFT

Urgency: Standard

General Description:
This Answer Record lists the known issues addressed in the D_IP1 IP Update.

Solution

GENERAL KNOWN ISSUES

Software Compatibility

The D_IP1 IP update is only compatible with Xilinx CORE Generator v3.1i (which is included with the Alliance v3.1i, Foundation v3.1i, and Foundation ISE v3.1i software). This IP update should not be used with any other versions of CORE Generator (such as v2.1i or earlier).

NOTE: Some data sheets may still refer to these cores as being compatible with v2.1i; however, this information is incorrect and will be updated in the next release.

Service Pack Requirement

D_IP1 has been tested with Service Pack 1 for the Xilinx v3.1i software. Service Pack 1 must be installed before installing D_IP1.

Service Pack 1 for v3.1i is available at:
http://support.xilinx.com/support/techsup/sw_updates/

Verilog and VHDL Model Delivery and Compile Order

Beginning with D_IP1 and the 3.1i Xilinx software release, compile order information is now documented for each IP release in the respective analyze order files:

$XILINX/verilog/src/XilinxCoreLib/verilog_analyze_order
$XILINX/vhdl/src/XilinxCoreLib/vhdl_analyze_order

The HDL behavioral simulation models for the updates are also included in the IP update archives under:

$XILINX/verilog/src/XilinxCoreLib/ and
$XILINX/vhdl/src/XilinxCoreLib/

Verilog Model Race Conditions:

Running Verilog behavioral simulation may cause race conditions for some cores. Affected cores are:

Adder Subtracter v2.0
Asynchronous FIFO v2.0
Bit Gate v2.0
Comparator v2.0
DA FIR Filter v3.0
Distributed Memory v2.0
Dynamic Constant Coefficient Multiplier v2.0
FD Based Register v2.0
Variable Parallel Multiplier v2.0

The suggested work-around is to run post-NGDBuild simulation instead of behavioral simulation.

Virtex-II Support

New Virtex-II cores have been added to the D_IP1 IP update release; however, software support for placing and routing of Virtex-II designs is in Alpha release and will not be generally available until the end of the year 2000.

HP Platform Support

If you are running CORE Generator on an HP platform, CORE Generator may fail to generate larger cores.
Reference: (Xilinx Answer 9624)


KNOWN ISSUES - CORES

Block RAMs (Virtex-II)

1. For the D_IP1 release of the Virtex II Single Port Block Memory, the initialization of the output registers caused by a SINIT or GSR command may be incorrect when simulating with the VHDL behavioral model. This only occurs when the core is generated using the RAMB16_S9 primitive.
Reference: (Xilinx Answer 9648)

2. In the DIP_1 release of Virtex-II Single and Dual-Port Block Memory, the cores do not support the user-specified memory initialization. The Virtex-II Block Memory HDL simulation models initializes the memory to zero by default.

3. When compiling VHDL behavioral simulation models for Virtex-II Block Memories, a -93 Compliancy switch must be used.
Reference (Xilinx Answer 9734)

4. No RPM support exists.

5. No support exists for Falling Edge Clocks. If an inverted clock is desired, then you must invert it outside of the core module.

Block RAM (Virtex)

1. Single-Port Block RAM: Selecting Falling-Edge for the clock polarity from the GUI does not work. The work-around is to edit the XCO file and change the incorrectly set parameter, then regenerate the core using the modified XCO file.
Reference: (Xilinx Answer 9559)

2. No RPM support exists.

3. The use of MIF files to specify memory initialization values is no longer supported. Instead, please use the COE file for this purpose.

Asynchronous FIFO

1. The 2.0 version of the Asynchronous FIFO core does not support block memory implementations when targeted to a Virtex-II. Only distributed memory (LUT) FIFOs can be built when the target architecture is Virtex-II. (Virtex and Spartan-II families have both block memory and distributed memory support.)

2. Users wishing to perform back-annotated simulation should always use the .sdf file when simulating. If a purely logical back- annotated simulation is desired (i.e., post-NGDBuild, or post-MAP), then NGDAnno should be run WITHOUT the NGM file. To avoid use of the NGM file by NGDAnno when generating simulation netlists, do NOT enable the "Correlate Simulation Data with Input Design" option in the Design Manager GUI.

FFT (Virtex-II Only)

This issue involves place-and-route (PAR) for the 16, 64, 256 and 1024-point Virtex-II FFTs. Due to a problem with the PAR software, these cores cannot be routed with the current version of the Virtex-II software. As a result, for this release, the Virtex-II FFTs can only be used for behavioral simulation.

This problem does not affect the Virtex 16, 64, 256 and 1024 FFTs.

DA FIR

No RPM support exists.

Distributed Memory and RAM-based Shift Register

The .COE file format for these two cores has changed from previous releases. Existing .COE files may not work with cores delivered in D_IP1. The 3.1i CORE Generator Guide documents only the old format.
Reference: (Xilinx Answer 9639)

Shift_RAM, Bit_Mux, Bus_Mux (Virtex-II only)

The ability to create RPM logic for Virtex-II cores is not available at this time, despite the fact that the GUIs for these cores allow you to request the creation of an RPM.
Reference: (Xilinx Answer 9689)
AR# 9332
Date Created 08/31/2007
Last Updated 08/23/2002
Status Archive
Type General Article