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AR# 9366

3.1i Foundation ISE, 3.4 FPGA Express: Netlists always rewritten when using BLIS (Block Level Incremental Synthesis) in ISE

Description

Keywords: FPGA Express, BLIS, Block Level Incremental Synthesis, netlist, export

Urgency: Standard

General Description:

When using Block Level Incremental Synthesis (BLIS) flow with FPGA Express in Foundation ISE, all design netlists will be rewritten, even if the source for the given module has not been changed. While the timestamp on the netlists will be updated, unchanged modules will not be resynthesized, and therefore the BLIS flow will work as desired with the exception of the fact that the timestamps on the EDIF netlists will be updated (ie, the contents of the EDIF file will remain unchanged for those blocks whose source has not changed).

Solution

AR# 9366
Date Created 05/25/2000
Last Updated 08/11/2003
Status Archive
Type General Article