When can I perform the FPGA JTAG EXTEST, INTEST, SAMPLE, and PRELOAD operations?
For information regarding how to use the FPGA JTAG operations, and what the operations do, please refer to the Xilinx Application Note (Xilinx XAPP139): "Configuration and Readback of Virtex FPGAs Using (JTAG) Boundary-Scan".
The operations can be performed as follows:
1. Before configuration:
All Virtex JTAG instructions except USER1 and USER2 are available during this time. To keep the device out of configuration mode, hold INIT Low and PROGRAM High. If PROGRAM is Low, no JTAG operations will work.
2. During configuration:
No JTAG operations can be performed during device configuration
3. After configuration:
All Virtex JTAG operations are available after configuration, including the USER1 and USER2 functions if so defined.