We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9410

12.1 Timing Closure - Suggestions for high fanout signals


I placed a timing constraint on a path, but the constraint has errors. What can I do to make this timing constraint pass?


Possible suggestions for high fanout signals:
  • Floorplan or LOC the origin and the global buffer of the high fanout signal.
  • Duplicate the driver and tell the synthesis tool not to remove the duplicate logic.
  • Use specific net fanout control on the specific net, if the synthesis tool allows.

For additional suggestions and recommendations, see the following Answer Records:
AR# 9410
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less