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AR# 9414

12.1 Timing Closure - Suggestions for paths through TBUFs or other intermediate points


I placed a timing constraint on a path, but the constraint has errors. What can I do to make this timing constraint pass?


Is this a valid path? Sometimes a path through a TBUF is not valid. You can create a new time spec to ignore this path with the following syntax:
FROM FFS THRU <output of tbuf> TO FFS TIG;
If this is a valid path from FFS through the TBUFs to FFS, then create a new time group. There are two ways to create a time spec to cover this path: (Comment = #)
#Creating a New Group;
INST flip_flop_names TNM = new_group;
#Exclude valid FFS from FFS group:
TIMEGRP new_group = FFS EXCEPT valid_ffs;
#Time spec Ignore:
TIMESPEC TS_TIG = FROM FFS THRU "output of tbuf" TO new_group TIG;
For additional suggestions and recommendations, see the following Answer Records:
- Suggestions for avoiding high fan-out signals, see (Xilinx Answer 9410).
- Suggestions for state machine optimization, see (Xilinx Answer 9411).
- Suggestions for long carry logic chains, see (Xilinx Answer 9412).
- Suggestions for I/Os 3-state enable paths, see (Xilinx Answer 9413).
- Suggestions for timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415).
- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416).
- Suggestions for how to avoid having too many levels of logic, see (Xilinx Answer 9417).
- Suggestions for timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418).
- Suggestions for timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419).
AR# 9414
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article
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