UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9438

3.1i XST - XST does not see Verilog meta comments in files originating from `include statements.

Description

Keywords: XST, meta, comments, Verilog, Synplicity, Synplify, attribute, passing, 3,1i, include

Urgency: Standard

General Description:
When I use meta comments in files that are brought into a project via a TCL-based `include statement, the meta comments are ignored without any error or warning being reported.

For example, a file design.v has `include "C:/main_mod.v" (note that there is a "/' instead of an MS-DOS-based '\"), where main_mod.v has a meta comment similar to <// synthesis attribute keep of tmp is true>. The meta comment will be ignored.

Solution

This problem is fixed in the latest 3.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 3.1i Service Pack 6.
AR# 9438
Date Created 06/06/2000
Last Updated 08/20/2002
Status Archive
Type General Article