In the Virtex-E data sheet, the input clock period tolerance is listed as 1 ns. What happens when the input clock period drifts more than this tolerance specification?
According to (Xilinx XAPP132), the DLL operates correctly up to the maximum period drift of 1 ns. If the input period drifts beyond this specification, the DLL will produce an unreliable lock signal and unreliable output clock. To recover from this condition, the DLL must be manually reset. Refer to (Xilinx XAPP132) for more information on using the RST pin of the DLL.