We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9461

3.x FPGA Express - Can I compile VHDL files from the command line or FE_SHELL?


Keywords: FE_SHELL, VHDL, command, line, compile

Urgency: Standard

General Description:
Can I compile VHDL files from the command line or FE_SHELL?


If you created your design in the GUI, you can obtain a script of the basic processes that were run by following the steps below:

1. Highlight the "Optimized" chip.
2. Select the "Script" pull-down menu.
3. Select "Export FPGA Script ..."
4. Choose the directory to where you want your script saved.

The following syntax illustrates how to compile VHDL files at the command prompt using FE_SHELL. The order of commands is as follows:

- Create a new project
- Add a source file
- Analyze it
- Create a chip for a specific architecture (in the following example, Virtex is used)
- Optimize the design
- Export the netlist

fe_shell > create_project -dir . fesproj
fe_shell > add_file prep4.vhd
fe_shell > analyze_file
fe_shell > create_chip -target VIRTEX -name p_v prep4
fe_shell > current_chip -name p_v
fe_shell > optimize_chip -name prep4_opt
fe_shell > export_chip
fe_shell > quit

For more information on all of the FE_SHELL commands, please see (Xilinx Answer 2061).
AR# 9461
Date Created 06/08/2000
Last Updated 08/11/2003
Status Archive
Type General Article