UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9469

9.1i Virtex PAR - "Error: place:1726 - Could not find an automatic placement for the following component...BUFG, CLKDLL"

Description

When I run my Virtex, Virtex-E, or Spartan-II design through PAR, the following error is reported: 

 

"Error: place:1726 - Could not find an automatic placement for the following component ... <list of components, including BUFG and CLKDLLs>."

Solution

This error occurs when the components in the DLL configuration cannot all be placed on the same edge of the chip, either because of partial constraints or because the sites are not available. 

 

To work around this problem, constrain all components mentioned in the error message; you can accomplish this by applying a LOC constraint to all CLKDLLs and associated BUFGs that are used in your design. 

 

Place the following syntax in the UCF: 

 

INST <DLL_instance> LOC = DLL<x>; 

INST <BUFG_instance> LOC = GCLKBUF<x>; 

 

where <x> is 0 to 3 for Virtex. 

 

For Virtex-E: 

 

INST <DLL_instance> LOC = DLL<x><y>;  

INST <BUFG_instance> LOC = GCLKBUF<x>; 

 

where <x> is 0 to 3 and <y> is P or S (primary or secondary).

AR# 9469
Date Created 08/21/2007
Last Updated 05/14/2014
Status Archive
Type General Article