I have a series of internal flip-flops in my design. When I implement my design, these FFs are optimized into an SRL16 inside the part. This sometimes causes worse timing than if only flip-flops were used. How do I prevent this from happening?
An SRL16 or SRL16E will be inferred if there is no reset term. To keep flip-flops out of the LUT, put a reset term on them.
If you do not use the reset term, connect it to a dummy signal and prevent the dummy signal from getting optimized out by putting an appropriate "KEEP" attribute for your synthesis tool on the net.
A "KEEP" property on the signals between registers should prevent them from being merged into a single slice.
The UCF syntax should be as follows:
NET "net_name" KEEP;