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AR# 9648

3.1i D_IP1 Virtex-II, CORE Generator - The output initialization for a single-port block RAM VHDL behavioral model is incorrect


Keywords: Virtex-II, COREGen, single, port, block, memory, VHDL Behavior Model, RAMB16, functional simulation, initialization

Urgency: Standard

General Description
For Virtex-II Single Port Block Memory, the output initialization for the VHDL behavioral model is incorrect. (This occurs when the generated core uses at least one or more RAMB16_S9 primitives.)

To verify that your core uses the RAMB16_S9 primitive, search for the string "RAMB16_S9" in the EDIF netlist generated by CORE Generator. The problem only occurs when the initialization value is expected at the memory output (e.g., when the GSR or SINIT input is active).

This failure does not affect the contents of the memory or other memory functions. The VHDL behavioral model may or may not fail, depending upon the actual initialization value. The generated netlist is not affected by this condition and will always function correctly in the actual device. The VERILOG behavior model does not display this condition.


Behavior simulation will not be successful in this situation; instead, use Post-NGDBuild, Post-MAP, or Post-Place and Route simulation.

Please see (Xilinx Answer 8065) for information on generating Post-NGDBuild simulation files.
AR# 9648
Date Created 07/06/2000
Last Updated 08/23/2002
Status Archive
Type General Article