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AR# 9658

3.1i CPLD TAEngine - Fails to expand wild cards [*] when processing timing constraints

Description

Keywords: CPLD, bus expansion, timing, TAEngine

Urgency: Standard

General Description:
Wild cards are not expanded properly when processing timing constraints.
This results in timing constraints that are denoted as N/A in the Post-Layout
Timing Report.

Solution

This is fixed in the latest service pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
The first service pack containing the fix is Service Pack 1.
AR# 9658
Date Created 08/31/2007
Last Updated 11/26/2008
Status Archive
Type General Article