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General Description :
How do I perform timing simulation in Innoveda's
EProduct Designer?
The flow for simulation for your schematic with VHDL coregen is as follows:
1. Generate the edif netlist from the schematic.
2. For function simulation:
2a. See solution 4318 at
http://support.xilinx.com/techdocs/4318.htm
3. For timing simulation:
3a. Open the Xilinx Design Manager
3b. Under the simulation options generate a time_sim.edf
From the Design Manager
Design->Options->Edit Options
(simulation options under the heading "Program Options")
Simulation Data Options = EDIF (this will produce time_sim.edf)
4. Run NGDBuild
5. Run Map
6. Run Par
7. Run Timing
7a. At this point, time_sim.edf will be produced.
8. These are the same steps for a functional simulation; see
http://support.xilinx.com/techdocs/4318.htm
At the command line run
"edifneto -l xilinx time_sim.edf"
"ngdbuild -p <part> time_sim.edf"
"ngd2vhdl time_sim.ngd"
9. At this point, a VHDL file will be produced that can be simulated.
10. Open Speedwave
11. File->Analyze VHDL Design
11a. Create a project and simprim directory
11b. Add the source file
11c. Add the simprim files (simprim_VITAL.vhd,
simprim_Vcomponenets.vhd, and
simprim_Vpackage.vhd)
11d. Save the project
11e. Compile the simprim library, then the source file
12. At this point, you should be able to load the design
SpeedWave.
AR# 9665 | |
---|---|
Date | 02/26/2014 |
Status | Archive |
Type | General Article |