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AR# 9689

3.1i Virtex-II CORE Generator - No RPM is generated for shift_ram, bit_mux, bus_mux cores after I add the D_IP1 update

Description

Keywords: shift RAM, bit mux, bus mux, D_IP1, relationally placed macro, RM, Virtex-II, CORE Generator, RLOC

Urgency: Standard

General Description:
When I generate a Virtex-II shift_ram, bit_mux, or bus_mux in CORE Generator with the option "Create RPM-Logic" selected, the following message is reported:

"There is No RPM Logic to Display in the Core Viewer."

Additionally, there will be no RLOC in the EDIF file that is generated by CORE Generator. This is because the Xilinx Place and Route tool cannot route Virtex-II cores with RLOCs at this time. Therefore, the capability to create RPM logic has been deliberately turned off by the CORE Generator for Virtex-II.

(Virtex and Spartan-II cores do not have this problem.)

Solution

This problem was fixed when CORE Generator's ability to create RPM logic for Virtex-II cores was added when the Xilinx Place and Route tool became capable of routing Virtex-II RPMs.
AR# 9689
Date Created 07/12/2000
Last Updated 08/23/2002
Status Archive
Type General Article