We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9835

3.1i XST - Incremental Synthesis does not appear to work (only one EDIF file in the directory)


Keywords: incremental, synthesis, edif, vhdl, verilog, hdl, modular, design

Urgency: Standard

General Description:
The incremental synthesis option for XST does not appear to work as there is only
one EDIF file that goes through implementation.


XST will not run the incremental synthesis option if the top level edif file from a non-
incremental synthesis run already exists in the directory. The workaround is to
remove the single top level EDIF file and then re-run synthesis.
AR# 9835
Date Created 08/02/2000
Last Updated 08/20/2002
Status Archive
Type General Article