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AR# 9864

3.x FPGA Express - FPGA Express infers an "FDCPE" clock enable flip-flop instead of an "FDCE" (XC9500XL family)

Description

Keywords: FPGA Express, flip, flop, ff, flip-flop, FDCPE, FDCE, infer, 9500, XL, 9500XL, XC9500, XC9500XL, XC

Urgency: Standard

General Description:
When I write HDL that should infer an FDCE for an XC9500XL device, FPGA Express infers an FDCPE. (The FDCPE is a macro comprised of the primitive FDCP, plus other logic that does not use the dedicated clock enable line included in the XC9500XL family.)

The VHDL and Verilog code that should infer an FDCE is as follows:

VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity test is
port (data : in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic);
end entity;

architecture arch_test of test is
begin

process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q<=data;
end if;
end if;
end process;
end architecture;

Verilog:

module test(data,clk,en,q);

input data,clk,en;
output q;
reg q ;

always@(posedge clk) begin
if (en)
q <= data;
end
endmodule

Solution

If the FDCE is necessary, the only solution is to have instantiated it.

VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity ff is
port (data: in std_logic;
clk : in std_logic;
en : in std_logic;
q : out std_logic);
end entity;

architecture ff_arch of ff is

component FDCE
port (D : in std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
Q : out std_logic);
end component;

signal ground : std_logic;

begin

ground <= '0';

u1: FDCE port map(data,clk,en,ground,q);

end architecture;

Verilog:

module test(data,clk,en,q);

input data,clk,en;
output q;
reg q ;
wire ground=1'b0;

FDCE my_fdce(.D(data), .C(clk),.CE(en),.Q(q),.CLR(ground));
endmodule
AR# 9864
Date Created 08/07/2000
Last Updated 08/11/2003
Status Archive
Type General Article