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AR# 9872

SimPrim, Timing Simulation - Pulses are swallowed in timing simulation (Verilog)

Description

During Verilog timing simulation, some pulses are swallowed. The input to the component (for example, buffer) is good, but the output does not change on the simulator waveform.

Solution

The pulse-swallowing (pulse-filtering) phenomenon occurs on signals in timing (back-annotated) simulations when the pulse width is shorter than the delay on the input port of the component. For example, if a clock of period 5 ns (2.5 ns High/2.5 ns Low) is propagated through a buffer, but the PORT or IOPATH delay (in the SDF) for the input port of that buffer is greater than 2.5 ns, the output is unchanged in the waveform window (for example, if the output is "X" at the start of simulation, it will remain at "X").

Software Versions after 5.1i

In all software versions after 5.1i, most of the pulse-swallowing issues have been corrected for Verilog. This was accomplished by using the PATHPULSE construct to annotate an accurate pulse-swallowing value to the simulation models. This instructs the simulator to use the value specified by the PATHPULSE construct rather than to swallow pulses that are smaller than the IOPATH delay.

Unfortunately, simulators do not obey this construct when looking at PORT delays in the SDF file. Xilinx annotates all net delays as PORT delays in the SDF. Consequently, any pulse that is smaller than the net delay over which it travels is swallowed. There are only a few ways in which this might occur. One is clock routing on the global network. This was corrected in 5.1i SP3 by annotating the clock delay as an IOPATH delay through a buffer rather than an input PORT delay. The only other likely cause of this issue is long routing delays on reset lines.

If you experience pulse-swallowing because of long reset delays or for any other reason, try the following steps:

1. Right-click "GeneratePost_Place & Route Simulation Model" -> Properties -> Check "Insert Buffers to Prevent Pulse Swallowing" . Regenerate the model and rerun the simulation. If this does not work, open a WebCase and submit the design for investigation:

http://www.xilinx.com/support/clearexpress/websupport.htm

NOTE: This problem can occur in the latest version of ISE when targeting Virtex-4 devices.

To work around this issue, see the simulator switches described below.

NOTE: VCS does not obey the PATHPULSE construct for PORT delays or IOPATH delays. For VCS, use the switches described below.

Software Versions Prior to 5.1i

To work around this problem, use a simulator switch to model all PORT and IOPATH delays as TRANSPORT delays, which do not filter pulses out. However, use of these switches propagates all pulses, including glitches, that are swallowed in the hardware. To prevent these glitches from propagating, Xilinx recommends the use of Pulse Rejection switches in addition to the switches mentioned above, so that glitches can be filtered (swallowed) in simulation.

The switches for the commonly used Verilog simulators are as follows:

NOTE: These switches should be used only if a pulse-swallowing problem occurs in simulation. Xilinx does not recommend using these switches as default options for all designs.

MTI ModelSim:

+transport_int_delays

(This switch changes all IOPATH delays to TRANSPORT delays.)

+transport_path_delays

(This switch changes all PORT delays to TRANSPORT delays.)

+pulse_e/10

(Flags as error and drive X for any path pulse whose width is less than or equal to the percentage of the IOPATH delay specified by the 10 , but is still greater than the percentage of the module path delay by the number argument to the +pulse_r/number option. )

+pulse_r/10

(Rejects any pulse whose width is less than 10 percent of IOPATH delay.)

+pulse_int_e/10

(Same as +pulse_e option, except it applies only to PORT delays.)

+pulse_int_r/10

(Same as +pulse_r option, except it applies only to PORT delays.)

These switches can be added onto the VSim command line in ModelSim.

Cadence NC-Verilog:

NC-Verilog handles PATH and INTERCONNECT delays as TRANSPORT delays by default. However, pulse control limits must be specified in the simulator. Without these specifications, the simulator does not allow any pulses smaller than the delay to be passed through. The recommended settings for these switches are:

+pulse_e/10

(Flags as error and drive X for any path pulse whose width is less than or equal to the percentage of the IOPATH delay specified by the 10 , but is still greater than the percentage of the module path delay by the number argument to the +pulse_r/number option. )

+pulse_r/10

(Rejects any pulse whose width is less than 10 percent of IOPATH delay.)

+pulse_int_e/10

(Same as +pulse_e option, except it applies only to PORT delays.)

+pulse_int_r/10

(Same as +pulse_r option, except it applies only to PORT delays.)

Cadence NCELab:

NCELAB handles PATH and INTERCONNECT delays as TRANSPORT delays by default. However, pulse control limits must be specified in the simulator. Without these specifications, the simulator does not allow any pulses smaller than the delay to be passed through. The recommended settings for these switches are:

-pulse_e 10

(Flags as error and drive X for any path pulse whose width is less than or equal to the percentage of the IOPATH delay specified by the 10 , but is still greater than the percentage of the module path delay by the number argument to the

-pulse_r/number option. )

-pulse_r 10

(Rejects any pulse whose width is less than 10 percent of IOPATH delay.)

-pulse_int_e 10

(Same as +pulse_e option, except it applies only to PORT delays.)

-pulse_int_r 10

(Same as +pulse_r option, except it applies only to PORT delays.)

Synopsys VCS:

The following switches must be added to the command line of VCS:

+transport_int_delays

(This switch changes all IOPATH delays to TRANSPORT delays.)

+transport_path_delays

(This switch changes all PORT delays to TRANSPORT delays.)

+pulse_e/10

(Flags as error and drive X for any path pulse whose width is less than or equal to the percentage of the IOPATH delay specified by the 10 , but is still greater than the percentage of the module path delay by the number argument to the +pulse_r/number option. )

+pulse_r/10

(Rejects any pulse whose width is less than 10 percent of IOPATH delay.)

+pulse_int_e/10

(Same as +pulse_e option, except it applies only to PORT delays.)

+pulse_int_r/10

(Same as +pulse_r option, except it applies only to PORT delays.)

For more details on setting the values of the +pulse or +transport switches, refer to the appropriate vendor documentation.

AR# 9872
Date Created 08/21/2007
Last Updated 02/26/2013
Status Active
Type General Article