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Last 7 Days' Answers

AR #33071 - 11.2 Constraint System - Area group constraint with group setting and compression results in a syntax error
Last Modified: 2009-07-02 00:00:00.0

AR #30061 - LogiCORE OBSAI v1.2 - Release Notes and Known Issues for 10.1 IP Update 0 (10.1_IP0)
Last Modified: 2009-07-01 00:00:00.0

AR #30447 - 10.1 PlanAhead - "ERROR: [HD-Constr 0] Could not find net '<net_name>' (file = <file_name>.ucf, line = #)"
Last Modified: 2009-07-01 00:00:00.0

AR #30046 - 10.1 Timing Analysis/Floorplan Editor, Cross-Probing - Physical Path view does not match Translated Path view (cross-probe)
Last Modified: 2009-07-01 00:00:00.0

AR #32054 - XPS_LL_TEMAC_v1_01 - INFO:coreutil - License for component <xps_ll_temac_v1> not found
Last Modified: 2009-07-01 00:00:00.0

AR #32234 - Aurora 8B10B for Virtex-4 FX FPGA v3.1 - Release Notes and Known Issues for ISE 11.1 IP Update 1 (IP_11.1.1)
Last Modified: 2009-07-01 00:00:00.0

AR #33065 - QPro Virtex-II 1.5 V - Data Sheet Update
Last Modified: 2009-07-01 00:00:00.0

AR #23614 - 11.1 System Generator for DSP - Why does the design fail to generate when using an IP core such as the FIFO block, the FIR Compiler, etc.
Last Modified: 2009-06-30 00:00:00.0

AR #24977 - 10.1 NGDBuild - "ERROR:NGDBuild:973 - The BUFE is not supported in ..."
Last Modified: 2009-06-30 00:00:00.0

AR #30062 - 10.1 Constraints Editor/PACE/Floorplan Editor - Comma separated ranges are ignored
Last Modified: 2009-06-30 00:00:00.0

AR #30017 - 10.1 Floorplan Editor/Timing Analyzer CrossProbing - The Clock and Data Paths for an OFFSET constraint do not connect
Last Modified: 2009-06-30 00:00:00.0

AR #30285 - 10.1 Floorplan Editor - Cannot delete constraints in New Source Wizard
Last Modified: 2009-06-30 00:00:00.0

AR #30362 - 10.1 PACE - Unable to load Spartan-IIE or Spartan-3E/-3A device with -4Q speed grade
Last Modified: 2009-06-30 00:00:00.0

AR #30366 - 10.1 Floorplan Editor - Unable to see all Vref pins and right side I/O pins for Spartan-3, Spartan-3A, Spartan-3AN, and Spartan-3A DSP devices
Last Modified: 2009-06-30 00:00:00.0

AR #29683 - 10.1 Floorplan Editor/PACE/PlanAhead - Are multi-dimensional arrays supported?
Last Modified: 2009-06-30 00:00:00.0

AR #29734 - 10.1 Floorplan Editor - The XC3S50A-5TQ144 package is opposite to the one shown in the data sheet
Last Modified: 2009-06-30 00:00:00.0

AR #30199 - 11.1 Partition - Can I use Directed Routing constraints that cross the partition boundary?
Last Modified: 2009-06-30 00:00:00.0

AR #30198 - 10.1 Partitions - How do I add PULLUP and PULLDOWN constraints to my lower-level partition?
Last Modified: 2009-06-30 00:00:00.0

AR #30024 - 10.1 Floorplan Editor - I cannot see some of the pins that are LOC'ed in the UCF from the package view of Floorplan Editor
Last Modified: 2009-06-30 00:00:00.0

AR #30047 - 10.1 Timing Analyzer/Floorplan Implemented - Cross-Probe to the technology view brings up an empty page
Last Modified: 2009-06-30 00:00:00.0

AR #30048 - 10.1 Timing Analyzer/Floorplan Implemented, Cross-Probing - Constraints are not annotated to the "Translated Path in Technology View" when cross-probing from Timing Analyzer
Last Modified: 2009-06-30 00:00:00.0

AR #30154 - 11.1 PlanAhead - I cannot import an NCD file into the project
Last Modified: 2009-06-30 00:00:00.0

AR #31394 - 11.1 PlanAhead - "ERROR:XDL - XDL cannot run on a protected design" when using a Xilinx secure core
Last Modified: 2009-06-30 00:00:00.0

AR #31594 - 11.1 PlanAhead - What files does Technical Support need to help me with a PlanAhead issue?
Last Modified: 2009-06-30 00:00:00.0

AR #31716 - 10.1 PlanAhead - DRC Error "IOs placed on prohibited sites" on pin AC5 in Virtex-5 with FF1136 package
Last Modified: 2009-06-30 00:00:00.0

AR #31269 - 11.1 Constraints System - Cannot prevent a PERIOD constraint from propagating through a DCM, PLL, or DLL
Last Modified: 2009-06-30 00:00:00.0

AR #32188 - Serial RapidIO - Virtex-5 FXT core might show data errors and "input-error stopped" state
Last Modified: 2009-06-30 00:00:00.0

AR #32196 - Serial RapidIO v5.2 - Release Notes and Known Issues for ISE 11.1
Last Modified: 2009-06-30 00:00:00.0

AR #32195 - Serial RapidIO v5.2, v5.3 - Virtex-4 FXT 3.125G, 4x core might not meet timing
Last Modified: 2009-06-30 00:00:00.0

AR #32623 - 11.1 EDK - BSP generated for MontaVista 5.0.24 kernel fails to boot
Last Modified: 2009-06-30 00:00:00.0

AR #33008 - 11.1 EDK - The BSP with the UartNS550 for MontaVista 5.0.24 kernel fails to boot
Last Modified: 2009-06-30 00:00:00.0

AR #24615 - 11.1 Incremental Design/Partitions - What are Partitions and how do they work?
Last Modified: 2009-06-29 00:00:00.0

AR #24510 - 10.1 Floorplan Editor - Crossprobed path does not display all delay values
Last Modified: 2009-06-29 00:00:00.0

AR #24507 - 10.1 Floorplan Editor - The Color of the Area Group is rendered incorrectly
Last Modified: 2009-06-29 00:00:00.0

AR #24509 - 10.1 Floorplan Editor - When reading AREA constraints from the ucf, Size is blank in the DOL for Partitions/Hierarchicals Initially
Last Modified: 2009-06-29 00:00:00.0

AR #24625 - 10.1 PACE - PACE does not read all LOC constraints
Last Modified: 2009-06-29 00:00:00.0

AR #24564 - 10.1 Floorplan Editor - Why do I get DRC errors: "ERROR:FloorplanEditorC - MGT113AB_TXN<0> : Location constraint incompatible. Please check user IO direction and IOB type?"
Last Modified: 2009-06-29 00:00:00.0

AR #24565 - 10.1 Floorplan Editor - Why does the error "ERROR:FloorplanEditorC - 2 DRC errors or warnings found" occur even if there are DRC warnings?
Last Modified: 2009-06-29 00:00:00.0

AR #25050 - 11.1 PlanAhead - Does my PlanAhead version have to match my ISE version?
Last Modified: 2009-06-29 00:00:00.0

AR #29279 - 9.2 PACE - "ERROR:DesignEntry - Could not apply constraint..."
Last Modified: 2009-06-29 00:00:00.0

AR #30013 - 11.1 PACE - Some of the menu buttons do not show up when running on Vista 32
Last Modified: 2009-06-29 00:00:00.0

AR #32656 - ISE Design Suite 11 ChipScope Pro Update 2 (11.2) - README
Last Modified: 2009-06-29 00:00:00.0

AR #32927 - 11.x XST - What is new in XST for Virtex-6 and Spartan-6 devices?
Last Modified: 2009-06-29 00:00:00.0

AR #33061 - 11.2 iMPACT - The Flash/PROM is no longer selectable after PROM File Formatter is relaunched
Last Modified: 2009-06-29 00:00:00.0

AR #33062 - LogiCORE Turbo Product Code (TPC) Decoder v1.1 - Can the TPC Decoder target other devices beyond those listed on the Product Page?
Last Modified: 2009-06-29 00:00:00.0

AR #33063 - LogiCORE Turbo Product Code (TPC) Encoder v1.0 - Can the TPC Encoder target other devices beyond those listed on the Product Page?
Last Modified: 2009-06-29 00:00:00.0

AR #33064 - 10.1/11.1/11.2 ChipScope Pro - Analyzer - ERROR: Socket Open Failed. localhost/0:0:0:0:0:0:0:1:50001
Last Modified: 2009-06-29 00:00:00.0

AR #25385 - Virtex-5 GTP RocketIO - Special considerations for aligning commas to the least significant RXDATA byte
Last Modified: 2009-06-26 00:00:00.0

AR #31996 - LogiCORE FIR Compiler v4.0 - When the "Generate chan_in value in advance" parameter is used, why is the chan_in output delayed by the specified number of cycles, rather than being output early by the specified number of cycles?
Last Modified: 2009-06-26 00:00:00.0

AR #31794 - Platform Flash XL, EDK Support - How do I access the Platform Flash XL from an EDK design?
Last Modified: 2009-06-26 00:00:00.0

AR #32548 - 11 ISE - Known Issues for Project Navigator 11
Last Modified: 2009-06-26 00:00:00.0

AR #32634 - ISE Design Suite 11 DSP Tools (System Generator for DSP and AccelDSP Synthesis Tool) Update 2 (11.2) README
Last Modified: 2009-06-26 00:00:00.0

AR #32767 - SPI-4.2 Lite v5.1 - Release Notes and Known Issues for ISE 11.2
Last Modified: 2009-06-26 00:00:00.0

AR #32301 - 11.1 Licensing - Trouble shooting Xilinx Software License issues
Last Modified: 2009-06-26 00:00:00.0

AR #33051 - 11.1 Licensing - "ERROR: Non-activation-capable daemon activation invoked with non-client-request event type"
Last Modified: 2009-06-26 00:00:00.0

AR #33027 - 11.1 ISE - "Warning: The design xxx.ncd is not up to date and may have been generated by a previous implementation run..."
Last Modified: 2009-06-26 00:00:00.0

AR #32805 - 11.1 ISE - I do not see the State Diagram Editor (StateCAD) in ISE 11.1
Last Modified: 2009-06-26 00:00:00.0

AR #32969 - 11.1 ISE - Project Navigator on Linux will not launch after new installation
Last Modified: 2009-06-26 00:00:00.0

AR #32843 - 11.1 Constraints Editor - Option of deselecting the reference timespec is not available in the table
Last Modified: 2009-06-26 00:00:00.0

AR #32949 - 11.1 Timing - Negative "Delay" values for one of TIG constraints
Last Modified: 2009-06-26 00:00:00.0

AR #32953 - 11.2 Timing Analysis - Not correctly using attribute CLKFX_MD_MAX in the Clock Uncertainty equation
Last Modified: 2009-06-26 00:00:00.0

AR #32954 - 11.2 Timing - Derived clock report does not have clock name for Spartan-6 reference design
Last Modified: 2009-06-26 00:00:00.0

AR #32955 - 11.2 Timing Analyzer - Clock skew calculations ignores the PRIORITY keyword on the PERIOD constraint
Last Modified: 2009-06-26 00:00:00.0

AR #32956 - 11.2 Timing, Virtex-5 -There is no MAX PERIOD Component Switching Limit check on the CLKFBOUT of the DCM
Last Modified: 2009-06-26 00:00:00.0

AR #32957 - 11.2 Constraint System - Net PERIOD constraints are been pushed from the REFCLK input to the RXRECCLK output of GTP/GTX
Last Modified: 2009-06-26 00:00:00.0

AR #33007 - 11.1 Timing, Virtex-4 - "WARNING:Timing:3327 - Timing Constraint" - Component Switching Limit is limited by DLL portion of the DCM when both DLL and DFS DCM outputs are used
Last Modified: 2009-06-26 00:00:00.0

AR #33058 - 11 EDK - Why does VxWorks fail to read over an NFS connection?
Last Modified: 2009-06-26 00:00:00.0

AR #32389 - 11.1 ISE Design Suite Install - XilinxUpdate only works on the last set installed tools
Last Modified: 2009-06-26 00:00:00.0

AR #32387 - 11.1 ISE Design Suite Install - I have multiple installations of ISE 11.1, but I can only uninstall the last installed
Last Modified: 2009-06-26 00:00:00.0

AR #32717 - XtremeDSP Development Kit-IV ROHS Compliant - Why do I see a reduced SFDR performance on the output of my ADCs, than is described in the XtremeDSP Development Kit-IV User Guide?
Last Modified: 2009-06-26 00:00:00.0

AR #33059 - 11.2 System Generator for DSP - Why do I receive an error message that an unsupported version of ISE is found, even though I have ISE 11 installed?
Last Modified: 2009-06-26 00:00:00.0

 
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