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Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory

This page covers Memory Interfacing in UltraScale Devices using the Memory Interface Generator (MIG) in the Vivado Design Suite

IntroductionDate
 Memory Interface UltraScale Design Checklist 
 UltraScale Architecture FPGAs Memory IP Product Guide04/04/2018
 Creating a Memory Interface Design using Vivado MIG04/04/2018
 Designing with UltraScale Memory IP09/16/2014
 Memory Interface UltraScale IP Release Notes12/20/2017
 Supported Memory Interfaces and Data Rates 
Design RequirementsDate
 Input Clock Guidelines04/04/2018
 Memory Interface External Clocking03/15/2016
 PCB Guidelines for DDR4 SDRAM04/10/2018
 PCB Guidelines for DDR3 SDRAM04/10/2018
 DDR4 Pin Rules04/04/2018
 DDR3 Pin Rules04/04/2018
 I/O Planning for UltraScale Device Memory IP04/04/2018
 Designing for High Efficiency04/04/2018
 Calculating User Specified Pattern Efficiency Using the Memory IP Performance Testbench04/04/2018
 Designing with UltraScale Memory IP09/16/2014
 Importing I/O Ports for an Existing Pin-Out/Board04/04/2018
Interfacing to Memory Interface IPDate
 Interfacing to the Memory IP User Interface04/04/2018
 Interfacing to the PHY Only Interface04/04/2018
 Interfacing to the AXI4 Slave Interface04/04/2018
Simulating Memory Interface IPDate
 Simulating the Memory IP Example Design04/04/2018
 Vivado Logic Simulation Design Hub04/16/2018
Frequently Asked Questions (FAQ)Date
 Memory IP UltraScale Solution Center - Frequently Asked Questions (FAQ) 

Additional Learning Materials

Additional Learning Materials

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