7 Series

This data sheet contains the DC and switching characteristic specifications for the Artix™-7 FPGAs.

This overview outlines the features and product selection of the Xilinx® 7 series FPGAs: Artix™-7, Kintex™-7, and Virtex®-7 devices.

This data sheet contains the DC and switching characteristic specifications for the Virtex®-7 FPGAs.

This data sheet contains the DC and switching characteristic specifications for the Kintex™-7 FPGAs.

This advance specification includes information on the Artix™-7, Kintex™-7, and Virtex®-7 device/package combinations and maximum I/Os, pin definitions, ASCII pinout files, and pinout diagrams showing I/O banks, power and ground placement, and memory groupings.

This guide serves as a technical reference describing the 7 series FPGAs GTX/GTH transceivers.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

This guide describes the function and operation of the 7 Series FPGAs Integrated Block for PCI Express®, including how to design, customize, and implement it. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint configurations at speeds up to 5.0 Gb/s (Gen2), all of which are compliant with the PCI Express Base Specification, rev. 2.1. This solution supports the AXI4-Stream interface for the customer user interface.

This all-encompassing configuration guide includes chapters on configuration interfaces, multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques for Xilinx® 7 series FPGAs.

This guide serves as a technical reference describing the 7 series FPGAs clocking resources.

This guide describes the SelectIO™ resources available in the 7 series FPGAs.

This guide describes the 7 Series FPGAs block RAM and FIFO capabilities.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Xilinx® 7 series FPGAs.

This guide describes the DSP48E1 slice in 7 Series FPGAs and includes configuration examples.

This guide serves as a technical reference describing the Xilinx® 7 series FPGAs XADC, a dual 12-bit, 1 MSPS analog-to-digital converter with on-chip sensors.

Design File(s):

• Design file for UG480

This guide serves as a technical reference describing the 7 series FPGAs GTP transceivers.

This guide provides information on PCB design and pin planning for 7 series FPGAs, with a focus on strategies for making design decisions at the PCB and interface level.

This document describes how to migrate designs utilizing prior FPGA architectures to 7 series FPGAs for improved density (cost), performance, and power.

EN192: Errata for the Virtex®-7 FPGA CES devices.

EN171: Errata for the Kintex™-7 FPGA XC7K325T CES9937 devices.

EN172: Errata for the Virtex®-7 FPGA XC7VX485T CES9937 devices.

EN179: Errata for the Kintex™-7 FPGAs XC7K480T CES9937 devices.

EN195: Errata for the Virtex®-7 FPGA XC7VX485T CES9900 devices.

EN180: Errata for the Virtex®-7 FPGA CES9937 devices.

EN183: Errata for the Kintex™-7 FPGA CES devices.

EN190: Errata for the Kintex™-7 FPGA CES9925 devices.

EN206: Errata for the Virtex®-7 FPGA XC7VX690T CES9937 devices.

EN193: Errata for the Virtex®-7 FPGA XC7VX485T CES9925 Errata devices.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Kintex-7 devices and related issues that impact Kintex-7 FPGA designs.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. 

This Design Advisory covers the Virtex-7 FPGA and related issues which impact Virtex-7 FPGA designs.

The USR_ACCESS register, present in the Virtex®-5, Virtex-6, and all 7 series FPGAs, provides the ability to embed version information into a 32-bit fabric-accessible register at the bitstream generation phase, allowing for the best balance of flexibility for the user with minimal impact to the design and implementation time.

This application note provides anti-tamper (AT) guidance and practical examples to help the FPGA designer protect the intellectual property (IP) and sensitive data that might exist in an FPGA-enabled system.

The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems.

This application note describes a ten data channel SFI-S design targeting Xilinx 7 series FPGAs using GTX or GTH serial transceivers to implement an aggregate 111.8 Gb/s bidirectional interface.

This application note describes a method for defining the hierarchical regions of interest in a user design and identifying the prioritized essential bits associated with the defined user logic using the ISE® design tools, version 13.4 and later.

Design File(s):

• xapp538.zip

This application note describes a method of capturing asynchronous communication using LVDS with SelectIO™ interface primitives. The method consists of oversampling the data with a clock of similar frequency (±100 ppm).

Design File(s):

• xapp523.zip

This application note covers the design considerations of a video system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp741.zip

This application note demonstrates the creation of video systems by using Xilinx native video IP cores such as AXI Video Direct Memory Access (VDMA), Video Timing Controller (VTC), test pattern generator (TPG), and the DDR3 memory controller to process configurable frame rates and resolutions in Kintex™-7 FPGAs.

Design File(s):

• xapp742.zip

This application note explains the benefits of using the voltage-identification technique to reduce power consumption and system costs.

Design File(s):

• xapp555.zip

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the 7 series FPGAs mixed-mode clock manager (MMCM). Similarly, the phase-locked loop (PLL) can be changed through the dynamic reconfiguration port (DRP). An explanation of the behavior of the internal DRP control registers is accompanied by a reference design that uses a state machine to drive the DRP, which ensures the registers are controlled in the correct sequence.

Design File(s):

• xapp888.zip

100% Material Declaration Data Sheet, FFG900 Package

Design File(s):

• IPC-1752 Form

This advance specification includes information on the Artix™-7, Kintex™-7, and Virtex®-7 device/package combinations and maximum I/Os, pin definitions, ASCII pinout files, and pinout diagrams showing I/O banks, power and ground placement, and memory groupings.

This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, Virtex-6, and 7 series FPGAs and provides the guidelines on how to use the SPI-4.2 DPA solution.

Xilinx's Agile Mixed Signal technology offers a better way to scale and customize common analog interfaces requirements. This technology is a unique combination of a flexible analog interface (XADC block) and the programmable logic capability of 7 series FPGAs and Zynq™-7000 Extensible Processing Platform (EPP).

This white paper explores the technical and economic challenges that led Xilinx to develop stacked silicon interconnect technology and innovations that make it possible.

Floating-point arithmetic, long the realm of general-purpose CPUs, DSPs, and graphics processing units (GPUs) is seeing growing use in FPGAs. Xilinx System Generator for DSP™ now meets this demand by supporting the design and implementation of floating-point algorithms from within the MathWorks Simulink modeling environment.

The purpose of a Power Distribution Network (PDN) is to provide power to electrical devices in a system. If a user determines the self-impedance (frequency) and knows the current (frequency) of the PDN, then the voltage (frequency) can be determined. The self-impedance (frequency) can easily be determined by simulating the frequency domain self-impedance profile of the PDN and is, thus, the subject of this white paper.

The architectures of the Xilinx® 7 series FPGAs feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

This white paper focuses on a dualport 100G gearbox implementation on a Virtex®-7 FPGA.

This white paper describes the features of the configurable logic block in the 28 nm Xilinx 7 series FPGAs, highlighting advantages over previous Xilinx FPGAs and the benefits that these changes bring to the digital design engineer.

This white paper provides an introduction to the benefits and features of the XADC and Agile Mixed Signal solutions implemented with Artix™-7, Kintex™-7, and Virtex®-7 FPGA families, and the Zynq™-7000 Extensible Processing Platform (EPP).

Xilinx® Plug-and-Play IP, together with its high performance, FPGA optimized, on-chip AXI4 interconnects, provides a simple yet powerful capability that can connect single or multiple sets of master and slave design blocks with a minimal amount of design effort.

The effective implementation of emphasis and equalization in Xilinx® 7 series FPGAs and Zynq™-7000 Extensible Processing Platform (EPP) is the subject of this white paper.

This white paper describes how the available Kintex-7 XC7K325T FPGA can be used as a hardware emulation platform for designs that will ultimately target Artix-7 FPGAs.

Xilinx has made significant investments in research and testing to offer customers a full range of SEU mitigation options as well as the lowest intrinsic FIT rates in the industry.

Vivado™ Design Suite is a new IP and system-centric design environment that accelerates design productivity for the next decade of All-Programmable devices.

This white paper describes several aspects of power related to the Xilinx® 28 nm 7 series FPGAs, including the TSMC 28 nm high-k metal gate (HKMG), high performance, low power (28 nm HPL or 28 HPL) process choice.

The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. Xilinx® Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques.

Three innovative Xilinx product families leverage the unprecedented power, performance, and capacity enabled byTSMC's 28 nm high-k metal gate (HKMG), high performance, low power (HPL) process technology and the unparalleled scalability afforded by the FPGA industry's first unified silicon architecture to provide a comprehensive platform base for next-generation systems.

The breakthrough combination of a high-performance, low-power process with architectural innovations makes new 28 nm FPGAs well suited for power-sensitive applications, bandwidth-intensive, and ultra-high-end applications.

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs.

This white paper addresses the flexible partial reconfiguration options when designing with 7 series, Virtex®-6, Virtex-5, and Virtex-4 FPGAs.

This white paper describes various memory interface and controller design challenges and the 7 series FPGA high-performance solution that achieves a 1.866 Gb/s DDR3 data rate for Virtex®-7 and Kintex™-7 FPGAs.

Since the introduction of the PCI Express® protocol, Xilinx has been the market leader in FPGA-based PCI Express solutions—from the soft IP FPGA logic-based solutions in the Virtex®-II Pro family, to the first Integrated Block for PCI Express in the Virtex-5 FPGA family, to its continued use in Virtex-6 and Spartan®-6 devices. The 7 series FPGAs will include the latest generation Integrated Block for PCI Express within a Xilinx FPGA. This breadth of experience has provided Xilinx the expertise to develop the easiest to use, most feature-rich, and highest performance PCI Express solution available.

Xilinx is responding to the demand for more bandwidth with two key developments. The first is high-fidelity 28 Gb/s transceiver technology. The second is 28 nm Virtex®-7 HT FPGAs that integrate an unprecedented 16 x 28 Gb/s and 72x13.1 Gb/s transceivers with logic, memory, and I/O resources that enable the first silicon device (FPGA orotherwise) to support 400G line cards and the industry’slargest single-FPGA solution for Nx100G line cards.

This white paper describes how the new I/O structures in the 7 series architecture support the range of performance and functionality challenges needed to address the broad range of application needs.