Aerospace QPro-R

This application note discusses different aspects of single-event upsets and recommends appropriate mitigation schemes under each circumstance.

This application note discusses self-hosting configuration management hardware setup for Xilinx® FPGAs for the purpose of detecting and correcting single-event upsets (SEUs) to the configuration memory array.

This application note describes mitigation techniques and corresponding design flow when using a Xilinx® FPGA with an embedded processor (specifically the PowerPC® 405 found in the Virtex®-4 FX family) in high-radiation environments.

This application note describes mitigation techniques using triple-module-redundancy (TMR) combined with configuration scrubbing for Xilinx®-specific block RAMs in high radiation environments. Also included is a design example demonstrating these mitigation techniques.