LVDS Application Notes

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The design takes advantage of the Virtex™-5 I/O ChipSync™ features ability to adjust the delay of the receiver datapaths creating dynamic setup/hold timing for each device at initialization, compensating for skews associated with the manufacturing process. The receiver operates at 1:8 deserialization on each of the 16 data channels.

Design File(s):

• xapp855.zip

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The receiver operates at 1:6 deserialization on each of the 16 data channels. Similar to XAPP855, the design also includes a real-time window monitoring circuit for added performance. This reference design calibrates and compensates for skews associated with process, voltage, and temperature (PVT) at initialization and dynamically during operation.

Design File(s):

• xapp860.zip

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

Design File(s):

• xapp491.zip
• xapp491.zip

The Spartan™-II and Spartan-IIE FPGA families simplify high-performance design by offering SelectIO™ inputs and outputs with programmable interface standards. This application note describes how to take full advantage of the flexibility of the SelectIO features and the design considerations to improve and simplify system-level design.

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

Design File(s):

• xapp880.zip

This Virtex™-5 application note describes an SFI-4.1 interface, a 16-channel, source-synchronous LVDS interface operating at SDR. The transmitter requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The receiver also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input.The timing of the receiver is described in depth and characterized in hardware.

Design File(s):

• xapp856.zip

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp485.zip

This application note describes how to interface a Fujitsu MB86064 digital-to-analog converter (DAC) with parallel low-voltage differential signaling (LVDS) inputs to a Virtex®-5 FPGA utilizing the dedicated I/O functions of the FPGA family.

Design File(s):

• xapp873.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp486.zip
• xapp486.zip

This application note describes how to utilize the dedicated deserializer(ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters that have parallel LVDS inputs.

This application note describes how to interface a Texas Instruments analog-to-digital converter (ADC) with serial low-voltage differential signaling (LVDS) outputs to Virtex®-4 or Virtex-5 FPGAs, utilizing the dedicated deserializer functions of both FPGA families.

Design File(s):

• xapp866.zip

This application note describes a method of capturing asynchronous communication using LVDS with SelectIO™ interface primitives. The method consists of oversampling the data with a clock of similar frequency (±100 ppm).

Design File(s):

• xapp523.zip