Application Notes

Describes the multipliers in the original Spartan®-3 FPGA architecture. For the Spartan-3E/-3A FPGA families, see the Multipliers chapter in User Guide UG331, Spartan-3 Generation FPGA User Guide.

Design File(s):

• xapp467_verilog.zip
• xapp467_vhdl.zip

This application note discusses an in-the-field upgrade of Virtex®-5 FXT bitstream, Linux kernel, and loader flash images using the presently running Linux kernel. Upgrade files are obtained from a USB mass storage device using the XPS USB Host core, or over the network from an FTP server.

Design File(s):

• Design Files for xapp1140.pdf

This Application Note describes a data capture technique for a high-performance DDR2 SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique can be used for memory interfaces with frequencies of 267MHz (533Mb/s) and above.

Previous generations of Xilinx® FPGAs supported a Master Parallel Configuration Mode which allowed the FPGA to configure itself directly from a parallel (byte wide) PROM. The Virtex® family of Xilinx FPGAs does not utilize a Master Parallel mode. This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.

Design File(s):

• xapp137.zip

The Xilinx® 2.1i development system adds Stamp Model Generation. This feature supports the use of board-level Static Timing Analysis tools, such as Mentor Graphics' Tau and Viewlogic's Blast. With these tools, users of Xilinx programmable logic products can accelerate board-level design verification.

Design File(s):

• xapp166.zip
• xapp166.tar.z

This application note demonstrates the process required to update a single design revision in a Platform Flash XCFP PROM using an IEEE Std 1149.1 Boundary-Scan (JTAG) Serial Vector Format (SVF) file.

This application note describes an implementation of a LIN controller on a Xilinx® CoolRunner™-II CPLD. A microcontroller interface is provided, but this could also be implemented as an IP core with minimal effort.

Design File(s):

• xapp432_lin_controller.zip
• xapp432_lin_io_module.zip

The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

Design File(s):

• xapp291.zip

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx® devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

The use of the internal IOB 3-state control register can significantly improve output enable and disable time. This application note illustrates the use of hard macros to implement this register in both HDL and schematic-based designs.

Design File(s):

• xapp123_make_macro.zip
• xapp123_make_macro.tar.z

This application note provides design advice for implementing arithmetic logic functions in two High-Level Design Languages (HDLs), VHDL and Verilog.

Design File(s):

• xapp215.zip
• xapp215.tar.gz

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Design File(s):

• xapp228.zip

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™-II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master. To obtain the VHDL code described in this document, go to section VHDL Code Download and Disclaimer, page 19 for instructions. This design fits XC2C256 CoolRunner-II or XCR3256XL CoolRunner XPLA3 CPLDs. For the CoolRunner-II CPLD version, refer to XAPP348, CoolRunner Serial Peripheral Interface Master.

Design File(s):

• xapp386.zip

This application note describes the use of configuration scrubbing and readback in the Virtex®-4 family of FPGAs for detecting and correcting single-event effects induced by cosmic rays.

Design File(s):

• xapp1088.zip

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

Design File(s):

• xapp931.zip

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note describes a system using the Virtex®-6 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx® Virtex-6 ML605 development board.

Design File(s):

• xapp1144.zip

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This application note describes the use of a Xilinx CoolRunner™ XPLA3 CPLD to implement a NAND Flash memory interface. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for memory interface applications.

This document details the VHDL implementation of an system Management Bus (SMBus) controller in a Xilinx CoolRunner™ XPLA3 256-macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SMBus controller.

Digital Up Converters (DUC) and Digital Down Converters (DDC) are key components of RF systems in communications, sensing, and imaging. This application note demonstrates how efficient DUC/DDC implementations can be created by leveraging Xilinx® DSP tools and IP portfolio for increased productivity and reduced development time.

Design File(s):

• xapp1113.zip

This application note describes an approach to the 3.3V configuration of Spartan®-3 FPGAs. It provides a set of proven connection diagrams for each configuration mode. The same approach can be applied to the Spartan-3E family.

UltraController-II is a minimal footprint embedded processing engine based on the PowerPC™ 405 (PPC405) processor core embedded within Virtex™-4 and Virtex-II Pro Platform FPGAs. System designers can easily incorporate the UltraController-II black-box processing engine into larger ISE designs to gain additional degrees of freedom by balancing usage of the high-performance FPGA fabric with the algorithmic flexibility of software.

This application note describes how to build a system that can be used for determining the optimal phase shift for a DDR memory feedback clock. In this system, the DDR memory is controlled by a controller that attaches to either the OPB or PLB and is used in an embedded microprocessor application. This reference system also uses a DCM that is configured so that the phase of its output clock can be changed while the system is running and a GPIO core that controls that phase shift. The GPIO output is controlled by a software application that can be run on a PPC or MicroBlaze™ microprocessor

Design File(s):

• xapp806_MB_ph_shift.zip
• xapp806_PPC_ph_shift.zip

This application note describes a system for accelerating BER measurements.

Design File(s):

• xapp948.zip

Checklist application note giving best practice CPLD design methodology.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

Design File(s):

• xapp482.zip
• xapp482.zip

In this application note, the triple error correcting Reed-Muller (RM) is implemented in both the Virtex™-II Pro and Virtex-4 Platform FPGA families.

Design File(s):

• xapp715.zip

This application note provides an introduction to the capabilities and functionality of the User Constraint File (UCF) for CoolRunner™ XPLA3 CPLD designs in WebPACK™ Project Navigator.

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This application note describes how to drive LEDs using Xilinx CPLDs.

This application note describes the steps for configuring the processor caches using the USR_ACCESS Register.

Design File(s):

• xapp719.zip

This application note describes how to build a Spartan™-3E embedded system that is used to determine the optimal phase shift of a DDR memory feedback clock.

Design File(s):

• xapp977.zip

This document contains detailed information related to the Virtex™-4 RocketIO™ Multi-Gigabit Transceiver (MGT) Static Operating Behavior described in EN014 (Errata for Virtex-4 FX CES2 and CES3 devices) and EN042 (Errata for Virtex-4 CES4 devices).

This application note contains additional information for designing with the XC3000™ series of FPGA devices. This information supplements the data sheets, and is provided for guidance only.

For the latest version of this application note, see the Multiplexers chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp466_vhdl.zip
• xapp466_verilog.zip

For the latest version of this application note, see the SRL16 chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp465_vhdl.zip
• xapp465_verilog.zip

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power™ (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX).

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™ CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX ).

This application note describes a DDR2 SDRAM memory interface for Virtex™-II Pro FPGAs.

For the latest version of this application note, see the Distributed RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp464_vhdl.zip
• xapp464_verilog.zip

The flexibility of the CoolRunner™-II CPLD allows users to configure any I/O pin to act as a voltage reference (VREF) pin. This document describes the different methods and underlying rules for determining the number and placement of these VREF pins.

This application note discusses the use of Xilinx XMD and GNU to debug software defects.

Design File(s):

• xapp1036.zip

This application note illustrates how to simulate PowerPC® 440 systems.

Design File(s):

• Design file for XAPP1003

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express® core. C code running on the PowerPC® 440 drives the EDK system.

Design File(s):

• Design file for XAPP1111

This application note demonstrates how to run a simulation of an EDK system containing the PLBv46 Endpoint Bridge for PCI Express®.

Design File(s):

• Design file for XAPP1110

This application note demonstrates how to access the In-System Flash in the Spartan™-3AN FPGA after the FPGA is configured.

Design File(s):

• XAPP1034 - Reference System: Accessing Spartan-3AN In-System Flash using XPS SPI

This application note outlines the techniques for debugging PowerPC® 440 processor systems in hardware and simulation.

Design File(s):

• xapp1060.zip

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This reference system demontrates improving system performance in the PowerPC® 440 Processor Block on the Virtex® -5 FXT FPGA.

Design File(s):

• xapp1121_nonopt.zip
• xapp1121_opt.zip

The Xilinx Spartan™-3A DSP FPGA features the ability to configure from standard serial flash over a built-in Serial Peripheral Interface (SPI). As general-purpose flash, the SPI serial flash can also be used for any other non-volatile storage that you might require. One such non-volatile purpose is the storage of MicroBlaze™ processor application code for bootloading.

Design File(s):

• xapp1053.zip

This application note demonstrates how to use a CoolRunner™-II CPLD as a Level Translator.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes XC4000XL/XLA and Spartan™-XL I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. However, such parameters are not production-tested and are, therefore, not guaranteed.

This 10-Gigabit Ethernet Hardware Demonstration Platform application note describes the functionality of the LogiCORE™10-Gigabit Ethernet and XAUI cores in Xilinx® FPGA hardware. It includes development board requirements, setup instructions, MAC core-specific design components, and a description of the graphical user interface used to control the demonstration platform.

Design File(s):

• xapp955.zip

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

This application note contains a reference design consisting of HDL IP and Xilinx® Advanced Configuration Environment (ACE) software utilities that give designers great flexibility in creating in-system programming (ISP) solutions.

Design File(s):

• xapp424.zip

Discovering electrical problems during the debug stage is too late. The printed circuit board has been built and may need significant changes to debug. The best approach is to avoid problems by planning for options at the outset. This application note provides a framework for checklisting a design early to eliminate problems.

This application note contains additional information that may be of use when designing with XC4000™ Series devices. This information supplements the product descriptions and specifications, and is provided for guidance only.

This application note discusses the usage of a Local Link DMA peripheral with the Linux operating system. A reference system with a Local Link DMA Loopback peripheral is included, as well as an example driver.

Design File(s):

• xapp1129.zip

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

Design File(s):

• xapp457.zip

This is a tutorial for building Linux kernels using the Xilinx® Git tree.

This application note describes a method for the reading and limited writing of small amounts of general-purpose user data into a Xilinx® Platform Flash XCF02S (2 Mbit) or XCF04S (4 Mbit) configuration PROM.

Design File(s):

• xapp544.zip

This application note provides an overview of the architecture and function of avionics full-duplex switched Ethernet (AFDX) as defined in the ARINC Specification 664, Part 7. It also describes how to map various functional blocks required for an AFDX end system to the Virtex®-4 and Virtex-5 architectures.

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

Design File(s):

• xapp694.zip

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

Design File(s):

• xapp500.zip

This Application Note describes the feature of Platform Flash PROMs that allows the user to Multiple-Boot or dynamically reconfigure from up to four Design Revisions.

Design File(s):

• xapp483.zip

The Spartan®-II and Spartan-IIE families provide fully digital Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system-level design.

Design File(s):

• xapp174.zip

This application note discusses Linux Operating System debugging techniques. Debugging boot issues, kernel panics, software and hardware debuggers, driver <-> application interaction, and various other tools are discussed.

Design File(s):

• Design Files for XAPP1137

Post-Configuration Access to SPI Flash Memory with Virtex®-5 FPGAs.

This application note provides the basic knowledge on how to integrate an embedded processor system with the Xilinx® Multi-Port Memory Controller (MPMC) and Video Frame Buffer Controller (VFBC) IP cores in System Generator for DSP (“System Generator”).

Design File(s):

• Design Files for xapp1136

This application note describes a reference design that adds fail-safe mechanisms to the MultiBoot capabilities of the Extended Spartan®-3A family of FPGAs. The reference design configures specific FPGA logic via an initial bitstream that determines which application to load.

Design File(s):

• xapp468.zip

This is an OPB PCI Reference design for use with the PPC405, Spartan™-II, or Spartan™-3 FPGAs.

Design File(s):

• xapp911.zip

This application note describes how the standard network performance suite Netperf is used to measure XPS LL TEMAC performance with MontaVista Linux 4.0.

Design File(s):

• xapp1127.zip

This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

Design File(s):

• xapp868.zip

Power consumption in Xilinx FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turn-off are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered to achieve successful designs.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

Relationally Placed Macros (RPMs) are frequently used in designs that have predefined modules or specific elements that need to be placed in such a way as to get highly predictable timing and performance. Floorplanner is a GUI-based tool that allows one to view and make these RPMs through the MacroBuilder capability. This application note explains the steps to create, instantiate, and implement a design with RPMs that were created in Floorplanner.

This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex™-5 XC5VLX330T FPGA.

Design File(s):

• xapp871.zip

This application note demonstrates using a Boundary Scan (JTAG) interface to configure and read back Spartan®-II and Spartan-IIE FPGA devices. Xilinx FPGAs have Boundary Scan features that are compatible with the IEEE Standard 1149.1. This application note is a complement to the configuration section in the Data Sheets and Application Note XAPP176.

This application note describes how to build a reference system for the PLBv46 PCI Core using the PowerPC™ 405 on the ML410 Embedded Development Platform.

Design File(s):

• xapp1001.zip

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

This document describes the features and benefits of the I/O cells provided by Xilinx® CoolRunner™ XPLA3 CPLDs.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For Virtex™ FPGAs, see XAPP135.) For additional data, see the Xilinx™ IBIS files.

This is a reference system for the OPB IIC on the ML402 Evaluation Platform.

Design File(s):

• xapp982.zip

This application note describes a low-profile In-System Programming solution, consisting of HDL IP and Xilinx® software tools, designed to handle only the JTAG functions needed for programming; resulting in less logic required and a smaller programming file compared to other full-featured solutions.

Design File(s):

• xapp975.zip

This application note describes a 200-MHz DDR SDRAM memory controller implemented in a Virtex™-5 device. This reference design uses the Virtex-5 ChipSync features to calibrate and adjust read data timing. A straightforward backend user interface is provided to allow integration into a complete FPGA design.

Design File(s):

• xapp851.zip

For the latest version of this application note, see the Block RAM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp463_verilog.zip
• xapp463_vhdl.zip

This document describes several different methods for interfacing 5V signals to CoolRunner™-II devices. These techniques may be used whenever voltage signal levels exceed the maximum input requirements of logic devices.

This application note describes how to use the XC9500™ timing model. All XC9500 CPLDs have a uniform architecture and an identical timing model, making them very easy to use and understand. To determine specific timing details, users need only compare their paths of interest to the architectural diagrams and, using the timing model presented here, perform a simple addition of incremental time delays.

This application note outlines three Galois multiplier solutions of increasing bit-length and complexity, stepping through generation and verification processes.

This application note describes the implementation of an Error Correction Control (ECC) module in a Virtex™-II, Virtex-II Pro, Virtex-4, and Virtex-5 device. The design can detect and correct all single bit errors (in a code word consisting of either 64-bit data and 8 parity bits, or 32-bit data and 7 parity bits), and it can detect double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

Design File(s):

• xapp645.zip
• xapp645.zip

This Application Note shows how to use the BDI-2000 Interface.

Design File(s):

• xapp981.zip

XC4000/XC5200/Spartan FPGA devices contain boundary scan facilities that are compatible with IEEE Standard 1149.1. This application note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design.

For the latest version of this application note, see the DCM chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

Design File(s):

• xapp462_verilog.zip
• xapp462_vhdl.zip

This application note discusses different aspects of single-event upsets and recommends appropriate mitigation schemes under each circumstance.

This document provides an overview of all Xilinx memory interface application notes that support Virtex™ Series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly.

This is the Xilinx® Dual Processor Reference Design suite that accompanies XAPP996 and WP262.

Design File(s):

• xapp996.zip

This is a reference design for the Spartan™-3E Display Development Kit to assist in developing display panel products. The display solution FPGA design consists of a Video Input interface, Color Temperature Correction, Precise Gamma Correction, Image Dithering Engine, and an output interface.

Design File(s):

• xapp928.zip

This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD.

Guided place-and-route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block(s), you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

Design File(s):

• xapp164.zip
• xapp164.tar.z

This application notes describes the CoolRunner™-II CPLD capability called “On the Fly”(OTF) Reconfiguration. OTF permits the CPLD to be operating with a design pattern and simultaneously acquire a second pattern during the operation of the first pattern. The second pattern can be configured into the device with a minimal disturbance to the operation of the device. Additional capabilities, applications and limits to this operation are discussed in further sections.

Frequently, the power voltage applied to a board is higher (or lower) than the nominal 1.8V VCCINT level required by CoolRunner™-II CPLDs. In these situations, power-ICs are commonly used to perform the required DC-to-DC conversion of the power voltage. These devices, known as regulators, take an unregulated input voltage and provide a regulated output voltage independent of input voltage variations or output current fluctuations. Many different types of regulators exist. This application note provides an explanation of each regulator type and presents some typical circuits to highlight currently available commercial regulators.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

The ITU-G.709 standard for error correction is examined and implemented in both the Virtex™-4 and Virtex-5 Platform FPGA families using the LogiCORE™ Reed-Solomon (RS) Encoder and Decoder cores.

Design File(s):

• xapp952.zip

This document provides an overview of Hardware Co-Simulation in System Generator for DSP from a performance perspective, and provides information to help reduce long simulation run times.

Design File(s):

• xapp1031.zip

This is an application note for programming serial Flash memory and the Strata Flash memory for the MicroBlaze™ Development Kit - Spartan®-3A DSP 1800A Starter Platform.

This application note describes how the standard network performance suite NetPerf is used to measure XPS LL TEMAC performance with Wind River VxWorks 6.3.

Design File(s):

• XAPP1063_ML405.zip

This application note helps designers get the best results from XC9500XL™ CPLDs. Included are practical details on such topics as pin migration, timing, mixed voltage interfacing, power management, PCB layout, high speed considerations and JTAG best practices.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes how to achieve low-cost serial configuration for Spartan™/Spartan™-XL FPGA designs, including: taking advantage of unused resources in a design (thereby reducing cost), part count, memory size, and board space. The idle processing time of an on-board controller is used to load configuration data from an off-board source, which allows a Spartan design to be upgraded in the field by sending the bitstream over a network.

This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. This note also discusses the functionality of the UART.

This application note describes difference-based partial reconfiguration. This type of reconfiguration is used when making small changes to design parameters including logic equations, filter parameters, and I/O standards.

This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan®-3A FPGA using iMPACT 9.1.01i. The hardware setup, software flows for file generation, and programming are also covered.

This application note discusses dynamic bus mode reconfiguration of PCI-X designs using LogiCORE™ solutions. It shows how to dynamically reload a Virtex™-4 and Virtex-5 FPGA after power-up using a CPLD to dynamically reconfigure the FPGA supporting PCI-X and PCI compatibility.

Design File(s):

• xapp938.zip

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner-II 256-macrocell CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 19 for instructions. This design fits both XPLA3 and CoolRunner-II CPLDs. For the CoolRunner XPLA3 CPLD version, please refer to XAPP333, CoolRunner CPLD I2C Bus Controller Implementation.

This application note discusses the use of the Xilinx Microprocessor Debugger (XMD) and the GNU software debugger (GDB) to debug software defects.

Design File(s):

• Design file for XAPP1037

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

Design File(s):

• xapp800.zip

This application note presents a design of a port expander that fits into a CoolRunner™-II XC2C32A device. The port expander is SMBus and I2C compatible.

Design File(s):

• XAPP799_designfiles.zip

Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain.

These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Design File(s):

• xapp689.zip

This application note describes the embedded PowerPC™ 405 (PPC405) processor in the Virtex™-4 FX FPGA and the main features of an APU-enhanced system. It includes examples illustrating the APU transfers data between the processor and the FPGA.

Design File(s):

• xapp717.zip

The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following: • Reduce total system cost by using less expensive devices • Achieve higher data transfer rates than allowed by specification • Add more loads to the bus to accommodate additional devices and connectors • Increase the physical length of the bus to accommodate novel bus topologies The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices.

This application note describes a simple CPLD-based interface design that configures a Spartan™-II device from a parallel EPROM using the Slave Parallel configuration mode.

This application note discusses typical curves that describe the output sink and source current for average processing, nominal supply voltage and room temperature for the Spartan™-II family of FPGAs. These curves are graphical representations of IBIS models, which are traditionally used for system and board-level simulation.

This document and the associated reference design provide guidance for assigning and debugging software to or in FLASH memory; specifically for a MicroBlaze™ embedded processor design.

Design File(s):

• xapp983.zip

The Spartan™-II FPGAs provide dedicated blocks of true dual-port RAM, known as Block SelectRAM+™ memory. This dedicated memory provides a cost-effective use of resources without sacrificing the existing distributed SelectRAM memory or logic resources. The Block SelectRAM+ memory is fully synchronous for easy timing analysis and is easily initialized at configuration. This additional integration capability makes the Spartan-II family ideal for cost-sensitive applications.

This application note shows how to connect an Intel Processor to a hard-disk drive.

Provides an overview of the baseband processing of a typical W-CDMA base station, along with the associated implementation challenges faced by W-CDMA equipment manufacturers, including the silicon cost, flexibility, and scalability trade-offs.

This application note describes a 3X-oversampling reference design that provides a 200 Mb/s to 1000 Mb/s serial interface using the Virtex™-II Pro RocketIO™ multi-gigabit transceiver (MGT). The reference design implements a 3X-oversampling circuit at the back end of the MGT and is targeted for the Fibre Channel rate of 1.0625 Gb/s.

Design File(s):

• xapp581.zip

The DEBUGHALT controller is a small, yet versatile piece of FPGA logic that simplifies the startup process of the PowerPC™ 405 (PPC405) processors in systems that cannot have any memory at the reset vector, or in systems that completely run out of cache. This application note is accompanied by a reference design that demonstrates debug halt mode implemented in the embedded PPC405 processor available on Virtex-II Pro™ FPGAs. The DEBUGHALT controller design enables external control of the PPC405 processor through the JTAG interfa

Design File(s):

• xapp571.zip
• xapp571.zip

Mixed signal systems require logic parts that can operate with two power supplies. XC9500™ CPLDs are designed to operate in either mixed 5V/3.3V systems or 5V-only systems. To handle both conditions, care has been taken to ensure that designers need not introduce elaborate circuitry to guarantee that 5V and 3.3V power supplies rise or fall in any particular sequence. This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these CPLDs.

This appnote shows how to use a CoolRunner™-II to interface with multiple SD cards.

Design File(s):

• xapp906_design_files.zip

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The design takes advantage of the Virtex™-5 I/O ChipSync™ features ability to adjust the delay of the receiver datapaths creating dynamic setup/hold timing for each device at initialization, compensating for skews associated with the manufacturing process. The receiver operates at 1:8 deserialization on each of the 16 data channels.

Design File(s):

• xapp855.zip

This application note describes the implementation of a Virtex™-4 RocketIO bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies non-encoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links between Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA.

Design File(s):

• xapp713.zip

This application note explains the techniques to support SATA initialization in the GTP transceiver of the Virtex®-5 LXT platform.

Design File(s):

• xapp870.zip

This application note describes how to simulate the LogiCORE™ IP IEEE 802.16e CTC Encoder and IEEE 802.16e CTC Decoder together using either ModelSim® or Hardware-in-the-Loop using Xilinx® System Generator software.

Design File(s):

• xapp1103.zip

This application note describes the implementation of a Smart Card Reader design with a CoolRunner™-II CPLD. Different from most of the software-based smart card reader computer systems, this CoolRunner-II CPLD implementation is a hardware solution. There is no software development needed in this design. This application note explains the low-level protocol of the Smart Card Reader and its hardware implementation.

This application note describes a reference design used to bridge one four-channel Xilinx SPI-4.2(PL4) core (v8.1) to four single-channel SPI-3 (PL3) Link Layer cores (v4.1), implemented in a single Virtex™-4 device.

Design File(s):

• xapp737.zip

This application note describes a DDR2 SDRAM interface implementation in a Spartan®-3 generation FPGA, interfacing with a Micron DDR2 SDRAM device. This document provides a brief overview of the DDR2 SDRAM device features, followed by a detailed explanation of the DDR2 SDRAM interface implementation.

This application note describes how to properly configure XC9500XL CPLDs in 5V/3.3V mixed systems, 3.3V-only systems, and 3.3/2.5V mixed systems.

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

Design File(s):

• xapp693.zip
• xapp693.zip

Uses CoolRunner™-II to control dot matrix LCD module. Includes design file.

Design File(s):

• xapp904_code.zip

This application note describes how C-to-HDL tools can easily create a hardware coprocessor from a critical function in the software system. The Auxiliary Processor Unit (APU) controller closely couples the embedded PowerPC™ processor and the Fabric Coprocessor Module (FCM), and provides a low-latency, high-bandwidth communication path. This application note demonstrates an accelerated Mandelbrot image generation application by moving computation-intensive functions to the hardware domain and attaching it to the PowerPC processor using the Virtex™-4 FX APU controller.

Design File(s):

• xapp901.zip

Power consumption in Xilinx Spartan™-II FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. It is common for a large, high-speed design to require one Ampere or more of current. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turnoff are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered in order to achieve successful designs.

This application note provides a reference design for point-to-point (FPGA to FPGA) high-speed serial packet transfer functionality using the integrated Endpoint block for PCI Express® designs in a Virtex™-5 LXT FPGA.

Design File(s):

• xapp869.zip

This reference system tests the operation of the OPB CAN core in loopback mode.

Design File(s):

• xapp913.zip

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

Design File(s):

• xapp229.zip
• xapp229.zip

The full throughput of a Virtex™-4 DSP48 slice can be achieved by time-multiplexing two data streams with a double data rate (DDR) technique. Alpha blending is an example of this technique. This application note describes an alpha blending reference design.

Design File(s):

• xapp706.zip

Implementation of a simple temperature controller in a CoolRunner™-II device.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices.

This application note illustrates how to measure the network performance of the XPS LocalLink Tri Mode Ethernet MAC (TEMAC) in an embedded processor system running the Treck TCP/IP stack.

Design File(s):

• xapp1043_mb.zip
• xapp1043_ppc405.zip

This application note shows how a Xilinx® CoolRunner™-II CPLD can be used as a simple logical switch that can quickly and reliably select between different MPEG video sources.

Design File(s):

• xapp944_source.zip.zip

This application note details an embedded system example design of a Web server running on the MicroBlaze™ soft processor, designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a Web client and how to connect to the Web server running on the MicroBlaze processor.

Design File(s):

• xapp433.zip
• xapp433.zip

This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder and discusses the reasons to use Manchester code. The code can be compiled into either the Xilinx XC9572 or XCR3064XL CPLD.

This application note outlines the various ways designers can utilize the DataGATE feature of CoolRunner™-II CPLDs.

The compatibility between the XC1700™ and XC18V00™ series of PROMs allows an engineer to take advantage of the in-system reprogramming features of the XC18V00 PROM during the development phase of a project and the lower cost benefit of an XC1700 series PROM during the production phase of a project. This application note discusses the considerations for systems that support a migration path from the XC18V00 PROM to an XC1700 series PROM. The topics include package compatibility, pin compatibility, I/O voltage compatibility, power and ground connections, and boundary-scan chain integrity.

This application note describes how to properly setup external and internal interrupts in an embedded hardware system. Use of an interrupt controller to manage more than one interrupt will also be included.

Design File(s):

• xapp778.zip

This application note provides a reference design for endpoint-initiated Direct Memory Access (DMA) data transfers using the LogiCORE™ Endpoint Block Plus for Virtex®-5 FPGAs.

Design File(s):

• xapp859.zip

This application note describes the implementation details of a bridge between a 133-MHz, 64-bit PCI-X interface and a 128 MB Double Data Rate (DDR), Small-Outline Dual Inline Memory Module (SODIMM) interface for Virtex™-4 devices. The reference design is capable of reading and writing up to four KB bursts of 64-bit data at 133 MHz.

Design File(s):

• xapp708.zip

Virtex™-4 ChipSync™ technology enables designers to create a wide variety of memory and networking applications. This document provides additional details on the ChipSync operation that are not covered in UG070: Virtex-4 UserGuide.

Using CoolRunner™-II CPLDs with standard chipsets.

This application note describes the probability of a metastable event occuring in a Xilinx Virtex™-II Pro FPGA. The test circuit measures the Mean Time Between Failure (MTBF) of these metastable events.

Internet Reconfigurable Logic (IRL™) is a system design methodology used to enable the remote upgrade of hardware while insuring the reliability of the upgrade. FPGAs, which are “Field Programmable”, are inherently capable of changing their functionality with a new bitstream. IRL takes advantage of this capability by delivering new bitstreams and software drivers to the remote hardware. This application note describes the basic concepts of an IRL-enabled system, detail design considerations for building an IRL system, and provides a high-level description of PAVE, the Xilinx API and development framework that enables embedded systems to be upgraded.

This application note describes various methods to configure Spartan™ series FPGAs. Each configuration method is described in detail. Information on necessary software programs to run with input files required, output files produced, download cables used, and other hardware necessary to accomplish the task is discussed. This application note targets users who are new to Xilinx® devices and Alliance/Foundation series software tools and is intended to make the configuration and debugging flows easy to understand.

Power consumption plays an important role in battery-powered applications. Spartan™-XL FPGAs are designed with segmented routing, 3.3-V operation, and advanced process technology to meet the needs for low power and high performance. This application note shows how to reduce power consumption by selectively disabling portions of the design that are not required all the time. This approach is particularly useful for devices that must be operating at all times. This application note discusses different strategies for reducing the supply current incrementally for an operating device.

This application note provides a functional description of Verilog source code for a keypad scanner.

Design File(s):

• xapp512__verilog.zip
• xapp512__verilog.zip

This application note describes how to connect Virtex™-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, and Spartan-3E devices to 3.3V or 5V PCI buses. The design responds to customer demand for a general solution for applications with a Virtex-II device and a 5V PCI bus, as well as for applications with a Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, or Spartan-3E device and a 3.3V or 5V PCI bus.

This application note describes how to build a reference system for the Processor Local Bus Peripheral Component Interconnect (PLBv46 PCI) Core using the MicroBlaze™ processor-based embedded system in the Avnet Spartan™-3 Evaluation Board.

Design File(s):

• Reference System: PLBv46 PCI Using the Avnet Spartan-3 FPGA Evaluation Board

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML505 Embedded Development Platform.

Design File(s):

• Design File for XAPP1030

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Design File(s):

• xapp225.zip

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

This application note describes a 267-MHz DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

MP3 portable players are the trend in music-listening technology. These players do not include any mechanical movements, thereby making them ideal for listening to music during any type of activity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music in a lot less space than current CD technology. Software is readily available to create MP3 files from an existing CD, and the user can then download these files into a portable MP3 player to be enjoyed in almost any environment.

This application note describes a reference system that demonstrates the use of the Multi-CHannel (MCH) On-chip Peripheral Bus (OPB) Double Data Rate (DDR) Synchronous DRAM (SDRAM) controller in a MicroBlaze™ processor system.

Design File(s):

• xapp912.zip

The Spartan™-II and Spartan-IIE FPGA families simplify high-performance design by offering SelectIO™ inputs and outputs with programmable interface standards. This application note describes how to take full advantage of the flexibility of the SelectIO features and the design considerations to improve and simplify system-level design.

This application note describes the implementation of a processor lockstep system using embedded PowerPC™ 405 (PPC405) processors in Xilinx Virtex™-II Pro FPGAs, along with Xilinx software tools. To verify lockstep functionality, users learn how to build and run the Linux operating system with the MontaVista Linux Preview Kit and also how to probe signals in the lockstep system with Xilinx ChipScope™ Pro tools.

Design File(s):

• xapp564.zip
• xapp564.zip

Describes the hardware accelerator for RAID6 parity generation / data recovery controller with ECC and MIG DDR2 controller.

Design File(s):

• xapp865.zip

On-die termination (ODT) promises higher signaling rates for printed circuit board (PCB) inter-chip interfaces through improved signal integrity. However, when using ODT, there is sometimes an associated power penalty. This application note explains the reason for the power penalty and suggests a simulation technique for comparing the signal integrity and power dissipation of internally and externally terminated versions of an interface.

Design File(s):

• xapp863.zip

Virtex™-5 devices have a high-precision programmable delay element (IDELAY) associated with every input pin. This application note shows how to implement 8X oversampling of many data streams using a single DCM, two global clock resources, and minimal FPGA logic resources. This solution provides better jitter tolerance than techniques using multiple DCMs. When paired with a suitable data recovery scheme, this oversampling technique can be used with many different data protocols up to 550 Mb/s. A reference design is included that implements a SD-SDI (SMPTE 259M) receiver running at 270 Mb/s.

Design File(s):

• xapp861.zip

This application note describes a 16-channel, source-synchronous DDR LVDS interface. The receiver operates at 1:6 deserialization on each of the 16 data channels. Similar to XAPP855, the design also includes a real-time window monitoring circuit for added performance. This reference design calibrates and compensates for skews associated with process, voltage, and temperature (PVT) at initialization and dynamically during operation.

Design File(s):

• xapp860.zip

This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Virtex™-4 PLB Tri-Mode Ethernet Media Access Controller(PLB_TEMAC).

Design File(s):

• xapp941.zip

Describes the Tri-Mode Ethernet MAC (TEMEC) UltraController-II module, which is a minimal footprint, embedded network processing engine based on the PowerPC™ 405 processor core and the TEMAC core embedded within a Virtex™-4 Platform FPGA.

Design File(s):

• xapp807.zip

This application note describes the DDR2 SDRAM physical layer design using the direct-clocking technique in a Virtex™-4 device. The direct-clocking technique utilizes some of the architectural features unique to the Virtex-4 family, for example, the 64-tap absolute delay line provided in each I/O block (IOB).

This application note describes the XC4000/Spartan™ Readback capability and its use. Topics include: initialization of the Readback feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading back FPGA devices, and Cyclic Redundancy Check (CRC).

Describes the bahavior of CPLDs during power up.

This application note provides a good guideline on PCB pad pattern design and assembling of QFN packages for optimal reliability and quality. This is only a guideline, and users are encouraged to perform actual studies to optimize the process.

This application note demonstrates how a CoolRunner™-II can be used as a power management device for multiple devices, including Virtex®-II and Spartan®:-3.

Hot-swapping or hot insertion describes a potentially dangerous method of inserting an unpowered board into a power-on (hot) running system. There are several concerns: the insertion must not cause physical harm or permanent damage to the system or the inserted board, and the insertion must not cause data corruption or any transient system upsets. This application note describes the physical aspects of hot-inserting a Virtex™-II based card into a system or system backplane, using sequenced connectors, where VCC and GND mate well before any signal pins can mate. The dangers of using normal non-sequenced connectors are described in Hot Plug-In. Not addressed in this application note are system issues including detecting the presence or absence of a card, or how the card is accepted in the system.

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

Design File(s):

• xapp953.zip

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

This application note describes a Redundant Array of Independent Disks (RAID) which is a hard-disk drive (HDD) array where part of the physical storage capacity stores redundant information. Data is regenerated from the physical storage if one or more of the disks in the array (including a single failed disk sector)or the access path to it fails.

Design File(s):

• xapp731.zip

This application note provides a quick and simple method for estimating power consumption of CoolRunner™ XPLA3 CPLDs. As an alternative to XPower, power can be quickly and easily computed using the equation and coefficients provided in this application note.

Describes the 3.3V PCI solution for the Virtex®-II Pro, Virtex-4, and Virtex-5 FPGA families.

This application note demonstrates the use of the Multi CHannel (MCH) On Chip Peripheral Bus (OPB) External Memory Controller (EMC) in a MicroBlaze processor system.

Design File(s):

• xapp923.zip

This application note is a reference system for the PLBv46 PCI core.

Design File(s):

• Design files for XAPP1057

This paper describes design practices to synthesize high density designs (i.e., over 100,000 gates), composed of large functional blocks, for today's larger Xilinx FPGA devices using the Synopsys FPGA Compiler. The Synopsys FPGA Compiler version 1998.02, Alliance Series 1.5, and the XC4000X family were used in preparing the material for this application note.

This application note describes system design techniques using a low power CoolRunner™ CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to offload operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings.

This application note demonstrates the use of the Multi-Channel OPB Synchronous DRAM controller in a MicroBlaze™ processor system.

Design File(s):

• xapp909.zip

The Xilinx Flip-Chip BGA package is the latest package offering for Xilinx high-performance FPGA products. Unlike traditional packaging in which the die is attached to the substrate face-up and the connection is made by using wire, the solder-bumped die-in Flip-Chip BGA is flipped over and placed face down, with the conductive bumps connecting directly to the matching metal pads on the laminate substrate.

For the latest version of this application note, see the IBIS chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

This application notes shows how to write stimuli in a high level language.

This application note is offered as complementary text to the configuration section of the Spartan®-II and Spartan-IIE data sheets and provides a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.

This application note describes the steps for using the different clocking resources on the XtremeDSP™ Development Kits developed by Nallatech.

Design File(s):

• xapp1005.zip

Some FPGAs require a minimum supply current in order to power on. For many applications, power supplies selected to cover operating current requirements can readily source enough instantaneous current to satisfy the power-on current requirement. For other applications, there may be a strict limit on the available supply current. The addition of a large capacitor and a few other passive components permit power-on with less supply current than the power-on specification requires. This application note presents a number of these “power-assist” solutions.

Design File(s):

• xapp451.xls
• xapp451.xls

FPGAs require a minimum supply current in order to power on. This application note explains the nature of the current, the implications of the power-on current specifications, and the major factors that influence the current. Board-level considerations and regulator selection follow. The last section introduces an approach to FPGA power-on in the presence of an overcurrent protection circuit.

This document details specific implementation techniques which may be used to decrease power consumption in CPLD designs.

This application note demonstrates the use of On-Chip Peripheral Bus (OPB) External Peripheral Controller (EPC) to support the SMSC LAN 91C111 controller chip in a PowerPC™ 405 processor based reference system.

Design File(s):

• xapp924.zip

The Ethernet Cores Hardware Demonstration Platform application note describes the functionality of Ethernet cores in Xilinx FPGA hardware. The development board requirements, setup and MAC core-specific design components are provided, as well as a description of the graphical user interface (GUI) used to control the demonstration platform. The platform demonstrates how to integrate these cores into a system, interface the Ethernet cores to a microprocessor, generate the required clock resources, handle the Ethernet data flow using packet FIFO and flow control, and connect to a physical interface.

Design File(s):

• xapp443.zip

Xilinx Alliance software version 3.3.06i (3.1i Service Pack 6) or later has been enhanced to include logical and timing cross-probing to Synplify™/Synplify Pro and LeonardoSpectrum™. The logical cross-probing feature enables the user to select instances or nets in warning or error messages in the Error Viewer to cross-probe back to the synthesis tool schematic view. This is useful for debugging a design with logical DRC errors/warnings. The timing cross-probing feature enables the user to select a path, nets, or instances to cross-probe from the timing report within Timing Analyzer back to the synthesis tool schematic view.

This describes how to use Create IP Wizard to create custom IP and how to then use it in EDK.

Design File(s):

• xapp967.zip

This application note describes how to build a reference system using the OPB PCI Core on the ML410.

Design File(s):

• xapp964.zip

CPLD design has advanced significantly beyond that of fast PAL design. Today's CPLDs must operate in systems that include microprocessors, memories, I/O devices, buses, multiple power supplies and multiple frequency clocks. The actual logic design is frequently minor with respect to the electrical issues that must be dealt with during debug.

This application note describes how to build a reference system for the PLBv46 PCI using a MicroBlaze based system in the ML555.

Design File(s):

• xapp999.zip

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

The Spartan-3A/3AN/3A DSP FPGA families offer an advanced static power management feature called Suspend mode, which reduces FPGA power consumption while retaining the FPGA’s configuration data and maintaining the application state. The device can quickly enter and exit Suspend mode as required in an application.

This application note discusses a reference design that demonstrates a logic-based, variable speed, three-phase AC induction motor controller.

Design File(s):

• xapp448.zip

This application note discusses system and FPGA design techniques for applications that operate in space or in other environments exposed to heavy ion or charged particle radiation. Single Event Upset (SEU) detection, correction, and mitigation for the XQR4000XL are demonstrated.

This is an OPB IIC reference design for the ML403.

Design File(s):

• xapp979.zip

This Application Note presents a method for doubling the frequency resolution of counter and timer applications using CoolRunner™-II.

This document describes the CoolRunner™-II timing model. Understanding the CoolRunner-II timing model is essential to creating a CPLD design that meets the desired timing requirements.

This application note describes a parameterizable 8b/10b Encoder and is accompanied by a reference design that replaces the 8b/10b Encoder core, previously delivered through the CORE Generator™ software.

Design File(s):

• xapp1122.zip

This application note discusses the designing of an EDK core with a LocalLink Interface.

Design File(s):

• xapp1126.zip

This application note provides a tutorial which covers the implementation of a simulated AC Induction motor driver; it is intended to serve as a very basic introduction for new users of Project Navigator.

Design File(s):

• xapp900.zip

This application note describes a reference system illustrating how to build an embedded PowerPC™ system using the Xilinx 1-Gigabit Ethernet Media Access Controller Processor Core.

Design File(s):

• xapp809.zip

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family.

This application note describes the implementation of an 8-bit microcontroller design using a CoolRunner™-II CPLD. The PicoBlaze™ Microcontoller instructions can be customized to make an application-specific microcontroller. CoolRunner-II devices, the latest CPLD family from Xilinx® offers both low power and high-speed performance. A complete VHDL code for PicoBlaze microcontroller design and C code for its assembler are available with this application note.

This application note describes how to run BFM Simulation of Processor Intellectual Property (PIP).

Design File(s):

• xapp516.zip

The purpose of this application note is to investigate the PCI (Peripheral Component Interface) environment when using 5 volt tolerant, 3.3 volt supply integrated circuits. In particular, we will examine the meaning of the statement "PCI compliant" when used in CPLD or FPGA data sheets.

This application note discusses the use of WindRiver VxWorks Real-Time Operating System on the Xilinx® ML403 board.

This application note describes mitigation techniques and corresponding design flow when using a Xilinx® FPGA with an embedded processor (specifically the PowerPC® 405 found in the Virtex®-4 FX family) in high-radiation environments.

Design File(s):

• xapp1004.zip

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML555 PCI/PCI Express Development Platform.

Design File(s):

• Design File for XAPP1000

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller.

This document provides a description of the CMOS output structures of the CoolRunner™ CPLDs and details some advantages of using true CMOS (rail-to-rail capable) output drivers.

This application note describes the use of partial reconfiguration in Virtex™ series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays. It is essential for the reader to have a basic understanding of the Virtex SelectMAP interface as well as configuration and readback operations. An in-depth review of Xilinx Application Note XAPP138 is highly recommended.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.

This application note provides a quick and simple method for estimating power consumption of CoolRunner-II CPLDs. As an alternative to XPower, power can be quickly and easily computed using the provided equation and coefficients as described in this application note.

This application note describes two reference systems illustrating how to build an embedded PowerPC® 405 system.

Design File(s):

• xapp1041_ppc.zip
• XAPP1041_mb.zip
• xapp1041_ppc440.zip

This reference system provides a mechanism to access the Ethernet PHY registers.

Design File(s):

• MicroBlaze files for XAPP1042
• PPC files for XAPP1042

This application note describes a CIO DDR RLDRAM II controller design implemented in a Virtex®-4 device.

This application note describes a DDR SDRAM controller implemented in a Virtex™-4 XC4VLX25 FF668 -10 device. This implementation uses direct clocking for data capture and an automatic calibration circuit to adjust delay on the data lines.

This application note describes mitigation techniques using triple-module-redundancy (TMR) combined with configuration scrubbing for Xilinx®-specific block RAMs in high radiation environments. Also included is a design example demonstrating these mitigation techniques.

Design File(s):

• xapp962.zip

This application note discusses self-hosting configuration management hardware setup for Xilinx® FPGAs for the purpose of detecting and correcting single-event upsets (SEUs) to the configuration memory array.

This application note discusses version 2.1i of the Xilinx Design Manager (DM) and Flow Engine (FE). In 2.1i, significant enhancements for DM/FE have focused on improving ease of use. A number of new features are provided, including "self-contained revisions" and the "Smart" Flow Engine.

This application note provides the necessary steps to get started with the EDK and Tornado 2.2.1/VxWorks 5.5.1 from installation to booting VxWorks on the ML300.

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

Design File(s):

• xapp491.zip
• xapp491.zip

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for controlling a serial ADC in a portable handheld application. This document provides an explanation of the VHDL code for the CoolRunner CPLD.

This application note provides a reference system for the PLB PCI on the ML410 Embedded Development Platform.

Design File(s):

• xapp945.zip

This application note describes the card-side implementation of an 16-bit CompactFlash (CF+)card interface using a CoolRunner™-II CPLD. Included in this implementation are the CIS, Attribute Memory Control and Status Registers, 16-bit Common Memory, and 8-bit I/O Interface. This design can be easily modified to interface to any memory, DSP or microcontroller.

This application note shows the connection of Xilinx® FPGAs to a Texas Instruments™ S320C6000 series Digital Signal Processor (DSP) using the available External Memory Interface (EMIF).

Design File(s):

• xapp753.zip

This application note discusses the use of Wind River VxWorks Real-Time Operating System (RTOS) on a ML507 board.

Design File(s):

• XAPP1114.zip

This application note describes a parameterizable 8b/10b Decoder, and is accompanied by a reference design that replaces the 8b/10b Decoder core, previously delivered through the CORE Generator™ software.

Design File(s):

• xapp1112.zip

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For other device families, see XAPP150.) For additional data, see the Xilinx IBIS files.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000™ Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. Emphasis is on the fast, efficient and reliable generation of the handshake signals FULL and EMPTY, which determine design performance.

This application note provides a basic outline for creating a cryptographic processor using CoolRunner™-II devices and a CPLD version of the PicoBlaze™ processor.

This application note demonstrates the use of the On-Chip Peripheral Bus (OPB) External Peripheral Controller (EPC) to support the Cypress CY7C67300 USB controller in a PowerPC™ 405 processor based reference system.

Design File(s):

• xapp925.zip

Guided place-and-route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block or blocks, you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

Design File(s):

• xapp165.zip
• xapp165.tar.z

With the release of M2.1i, Floorplanner supports the Virtex™ family of FPGAs. This application note illustrates how the major Virtex-specific architectural features, such as BlockRAMs, global clock buffers, DLLs, and carry logic, are represented within the Floorplanner GUI and how designers can manipulate a design containing these elements.

This application note presents information on version 2.1i of the FPGA Editor and how it differs from the previous version of EPIC. (For general FPGA Editor usage, refer to the FPGA Editor Guide.) This application note also discusses how to return to EPIC type actions for zoom and pan actions.

The 2.1i software includes improvements in the Trace, Timing Analyzer, FloorPlanner, Constraints Editor, and other implementation tools to help make the designing procedure easier for Virtex™ devices. This paper is devoted to describing some of the simple steps necessary to constrain a Virtex design with the 2.1i implementation tools. The paper explains how to constrain with a CLKDLL in Virtex and examines the new look of the Timing Analyzer Reports.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This application note describes the implementation and timing details of a four-word burst QDR II SRAM interface for Virtex®-4 devices. The synthesizable reference design leverages the unique I/O and clocking capabilities of the Virtex-4 family to achieve performance levels up to 300 MHz (600 Mb/s), resulting in an aggregate throughput for each 36-bit memory interface of 43.2 Gb/s.

This application note provides a detailed description of the Spartan®-3 FPGA family configuration architecture. It explains the composition of the bitstream file and how this bitstream is interpreted by the configuration logic to program the part.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

Design File(s):

• xapp211.zip
• xapp211.zip

This document provides a brief description of how to perform ISP operations with XPLA3 CPLDs.

This application note describes the use of the XC9500XL™ timing model.

This application note discusses XC9500XL CPLD power estimation and optimization and provides designers with an understanding of sense-amplifier-based CPLD power dissipation. The note also provides a brief discussion of the process for estimation. With this information, you can accurately assess the power dissipation for a design. Guidelines that permit you to make key choices to manage the power dissipation of your design and understand the package thermal limits are also presented.

This application note addresses low-cost, four- to six-layer, high-volume printed circuit board (PCB) layout for a Spartan™-3E FPGA in the FT256 1 mm BGA package. Intended for design engineers, managers, and PCB layout staff, who are already familiar with SI related design issues. The general guidelines can be used to optimize board layout for other devices and packages.

Design File(s):

• xapp489.zip
• xapp489.zip

This application note describes methods which will produce consistently fast designs when used with Xilinx® CoolRunner™-II CPLD family. More detail on this important new family of 1.8V CPLDs is available at the Xilinx Web site (www.xilinx.com), where the family and individual part data sheets can be found. Additional application literature is also available. Of particular interest is XAPP375, which discusses the timing of the CoolRunner-II CPLDs, and XAPP376, which discusses the basic operation of the macrocell and function block—the “logic engine” of the CoolRunner-II family.

This application note describes how to implement the CoolRunner™-II advanced features in the Xilinx software. These features include the DualEDGE triggered registers, clock divider, CoolCLOCK, DataGATE, Schmitt trigger inputs, and I/O termination types.

This application note illustrates the implementation of an IrDA and UART system using a CoolRunner™ XPLA3 CPLD. The note also describes the fundamental building blocks required to create a half-duplex IrDA and full-duplex UART interface design.

This application note focuses on the baseband demodulation of Quadrature Amplitude Modulation (QAM) signals and, more specifically, on the use of a fractional rate decimator block. This application note also reviews polyphase decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator 8.1i implementation, and its results.

Design File(s):

• xapp936.zip

The oversampling module described in this application note performs 3/4/5/6X oversampling. The oversampling ratio is selectable during operation to facilitate multi-rate applications. It is designed to accept 20 bits of oversampled data and to output 10 bits of extracted data to the user interface. This module can be used with the Virtex-II Pro™ RocketIO™ Multi-Gigabit Transceiver (MGT) to achieve line rates of 200 Mb/s to 1000 Mb/s.

Design File(s):

• xapp572.zip

This application note discusses XC9500XL™ device use in multi-voltage systems.

CoolRunner™-II RealDigital CPLDs are the only CPLDs to combine both high performance and low power to form the next generation CPLD. This application note describes the design methodologies that can be employed to obtain the lowest power possible using the CoolRunner-II CPLD by utilizing its unique power saving features.

CoolRunner™-II is the Xilinx® CPLD Family that raises the standard for Complex Programmable Logic Devices. CoolRunner-II delivers unmatched performance with the industry’s lowest power at highly competitive price points in an aggressive spectrum of packages. This application note details how CoolRunner-II CPLDs create logic within their CMOS fabric. In all likelihood, you will never need to know these details as the design software will automatically complete your design giving highest speed and lowest power with very little user direction. In the event that you would like to understand the inside details of how CoolRunner-II does its magic, this application note should help serve that need. For general CoolRunner-II information, also refer to the CoolRunner-II Family Data Sheet and individual device data sheets.

This application note details an embedded system example design of a web server running on a PowerPC™ core within a Xilinx Virtex™-4 FPGA. The system is designed using the Embedded Development Kit (EDK). The application note also explains how to set up a system as a web client and how to connect to the web server running on the PowerPC processor.

Design File(s):

• xapp434.zip
• xapp434.zip

This document presents design techniques and reference circuits that power Virtex™-4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

This application note describes how to modify an existing MicroBlaze™ processor design to support the trace features in MicroBlaze processor v7 and above.

Design File(s):

• xapp1029.zip

This application note provides information on using the PLB DDR2 with OPB Central DMA.

Design File(s):

• xapp935.zip

This application note provides an introduction to Nucleus RTOS on the MicroBlaze™ processor using Xilinx Platform Studio (XPS) tools and Mentor Graphics EDGE tools.

Design File(s):

• xapp1016.zip

Shift registers longer than eight bits can be efficiently implemented in XC4000™ or Spartan™ series SelectRAM memory. Using Linear Feedback Shift Register (LFSR) counters to address the RAM makes the design even simpler. This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers, and pseudo-random sequence generators with repetition rates of thousands and even trillions of years, useful for testing and encryption purposes. The appropriate taps for maximum-length LFSR counters of up to 168 bits are listed.

This application note helps guide designers in fitting designs into the smallest possible CPLD devices.

Design File(s):

• xapp444.zip
• xapp444.zip

Even after volume shipments have begun, customers can take advantage of the "In-System ECO" (Engineering Change Orders) capability in Virtex™-4 EasyPath FPGAs to make changes to LUTs and I/Os. This application note describes how to make these changes in a simple way using the FPGA Editor tool.

This document describes a reference design for interfacing CoolRunner™-II CPLDs with double data rate (DDR) SDRAM memory devices. The built reference design is capable of 100 MHz operation.

This application note describes the implementation of a single error correction, double error detection (SECDED) design with a CoolRunner™-II CPLD. CoolRunner-II devices are the latest CPLD from Xilinx® that offer both low power and high-speed performance. A complete VHDL design is available with this application note.

This document is designed to be a comprehensive description of the I/O structure of the CoolRunner™-II CPLD family. The I/O pins have the most dramatic externally observed behavior of any IC feature. This application note should help illustrate what the I/Os can and cannot do, as well as detail the limits of their drive and performance.

This document describes the demo board that uses the CoolRunner™-II 64-macrocell CPLD.

This document highlights the advantages of utilizing the universal control terms provided in the CoolRunner™ XPLA3 CPLD architecture. This application note also discusses design examples showing the efficiency of these universal control terms.

This application note describes power-up characteristics for CoolRunner™ CPLDs that may be of interest, depending upon where and how the devices are used.

This application note provides information on how to perform Express configuration for the Spartan™-XL family. Express Mode uses an eight-bit-wide bus for fast configuration of Xilinx FPGAs. The steps of Express configuration are described, followed by detailed circuit implementation instructions.

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Design File(s):

• xapp224.zip
• xapp224.zip

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

Design File(s):

• xapp223.zip

This Application Note discusses the procedures and some commonly asked questions related to the creation of pin placement prior to implementation. The procedures and questions are tailored to several applications of memory interfaces, LVDS interfaces, and other applications.

Design File(s):

• xapp423.zip

This application note discusses the fundamental flows of the Pinout Area Constraints Editor (PACE) tool. The PACE tool was created to simplify constraining tasks that are performed relatively early in the design process: I/O Pin assignment and Area Group creation. Widespread PACE usage is anticipated, especially for I/O Pin assignment, as all users must perform this task for every design. Rapidly increasing package sizes and I/O counts make PACE a particularly vital tool.

For the latest version of this application note, see the BSDL chapter in User Guide UG331, Spartan™-3 Generation FPGA User Guide.

This application note outlines how to successfully configure a Spartan™-3A FPGA from a Platform Flash PROM. Including hardware requirements and software flows for generating and programming PROM files.

This application note compares the performance between software and hardware implementations of an LPM algorithm. It shows how the hardware implementation, which uses the APU interface of Virtex®-4 FPGAs, outperforms the software implementations.

Design File(s):

• xapp738.zip

This document describes the macrocell configurations of Xilinx® CoolRunner™ XPLA CPLDs.

This application note shows how the 32-bit MicroBlaze™ processor can easily access wide data width memories. The design is also suitable for use with the IBM PowerPC™ (PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus.

Design File(s):

• xapp729.zip

This application note describes a 267 MHz (and above) DDR2 controller implementation in a Virtex™-4 device interfacing to a Micron DDR2 SDRAM device.

The application discusses the use of the Xilinx® Microprocessor Debugger (XMD) and the GNU software debugger (GDB) to debug software defects.

Design File(s):

• xapp1117.zip

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

Using and Creating Flash Files for MicroBlaze™.

This application note describes a system using the Virtex™-5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx® Virtex-5 ML505 development board.

Design File(s):

• xapp957.zip

This is a reference system for the OPB Ethernet MAC.

Design File(s):

• xapp942.zip

This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet (TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0.

Design File(s):

• xapp1023.zip

Describes how to implement a Virtex™-4 FX PowerPC™ 405 system with the Xilinx floating point unit (FPU) coprocessor.

Design File(s):

• xapp547.zip
• xapp547.zip

Spartan™-XL FPGAs come equipped with a Power Down mode that permits an exceptionally low level of power consumption (ICCO = 100 µA typical), making the family ideal for portable battery-powered applications. This application note provides all the information needed for a designer to use Power Down mode effectively, including descriptions of the mode's common applications, internal functioning and electrical characteristics.

This application note and reference design provide a digital phase-locked loop (DPLL) solution using minimal external components and spare Virtex™-4 resources. The performance of the DPLL is superior to most integrated mixed-signal solutions. The DPLL design can be used in many different applications, including jitter reduction PLLs, clock multiplier PLLs, clock recovery PLLs, and clock generators.

Design File(s):

• xapp854.zip

This application note documents using a Xilinx® CPLD as a motor controller.

Design File(s):

• xapp940.zip

This Application Note describes how to get started using Linux 2.6 and EDK.

Design File(s):

• xapp969.zip

This application note describes the controller and the data capture technique for high-performance DDR3 SDRAM interfaces. This data capture technique uses the Input Double Data Rate (IDDR) and Output Double Data Rate (ODDR) features available in every Virtex®-5 FPGA I/O.

Design File(s):

• xapp867.zip

The DDR2-400 (200 MHz clock) memory interface discussed in this application note is derived from the default output of MIG. Xilinx has validated this interface in Spartan®-3A FPGAs with the higher speed grade (-5) assembled on Spartan-3A Starter Kits. The validation results also apply to Spartan-3AN and Spartan-3A DSP FPGAs.

Design File(s):

• xapp458.zip

This application note describes methodologies for interfacing Virtex®-6 devices to 3.3V systems. It covers input, output, and bidirectional busses, as-well-as signal integrity issues and design guidelines.

This application note describes how to use a Virtex®-5 device to interface to Common I/O(CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices.

Design File(s):

• xapp852.zip

This application note provides designers using System Generator tools with options for source version control to determine the best tool flow and methodologies for team-based development.

Design File(s):

• xapp498.zip

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

Design File(s):

• xapp880.zip

This Virtex™-5 application note describes an SFI-4.1 interface, a 16-channel, source-synchronous LVDS interface operating at SDR. The transmitter requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The receiver also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input.The timing of the receiver is described in depth and characterized in hardware.

Design File(s):

• xapp856.zip

This application note describes how to indirectly program select BPI PROMs through the JTAG interface of a Virtex®-5 FPGA using iMPACT. The required hardware setup, BPI-UP PROM file generation, and the indirect programming flow are described.

This application note describes how to interface the Virtex®-5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC Standard No. 204A.

Design File(s):

• xapp876.zip

This application note provides a discussion of strategies and representative calculations for handling single event upsets (SEUs) with an emphasis on reliability when addressing these low probability events. This application note also introduces an SEU controller macro that can be included in any Virtex®-5 FPGA design to implement an SEU detection and correction scheme.

This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express® used in the Xilinx ML507 Embedded Development Platform.

Design File(s):

• xapp1040.zip

This application note describes an in-the-field upgrade of the Spartan®-6 FPGA bitstream, Linux kernel, and loader flash images, using the presently running Linux kernel.

Design File(s):

• xapp1146.zip

This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex®-6 XC6VLX240T FPGA.

Design File(s):

• xapp882.zip

This application note is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience. Testbenches are the primary means of verifying HDL designs. This application note provides guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to develop a self-checking testbench for any design.

Design File(s):

• xapp199.zip
• xapp199.tar.gz

This application note provides background on NSEUs in SRAM-based FPGAs, mitigation techniques (with a focus on configuration memory) suggested by Xilinx, and an overview of calculating projected failures-in-time (FIT) rates at altitude.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

Design File(s):

• xapp780.zip

This application note discusses how to efficiently use the Spartan®-6 FPGA ISERDES and OSERDES primitives in conjunction with the input delay blocks and phase-detector circuitry.

Design File(s):

• xapp1064.zip

This application note and associated reference design describes how to merge the operation of two or more Memory Controller Blocks (MCBs) to implement effective 32-bit or wider memory interfaces in Spartan®-6 FPGAs.

Design File(s):

• xapp496.zip

This application note describes the implementation and timing details of a four-word burst Quad Data Rate (QDR II) SRAM interface for Virtex®-5 devices.

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp485.zip

The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.

Design File(s):

• xapp997.zip

This application note describes how to interface a Fujitsu MB86064 digital-to-analog converter (DAC) with parallel low-voltage differential signaling (LVDS) inputs to a Virtex®-5 FPGA utilizing the dedicated I/O functions of the FPGA family.

Design File(s):

• xapp873.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp486.zip
• xapp486.zip

This application note describes how to utilize the dedicated deserializer(ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters that have parallel LVDS inputs.

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

This application note explains how to use the Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

Design File(s):

• xapp551.zip

This application note demonstrates how to efficiently implement Digitial Up and Down Converters(DUC/DDC) by leveraging the Xilinx® DSP IP portfolio. Two example DUC/DDC designs are provided for UMTS and CDMA2000 in both Spartan®-3A DSP and Virtex®-5 FPGAs.

Design File(s):

• xapp1018_cdma2000.zip
• xapp1018_wcdma.zip

This application note uses Virtex®-6 FPGA SelectIO™ technology to perform 4X asynchronous oversampling at 1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the mixed-mode clock manager (MMCM) dedicated performance path.

Design File(s):

• xapp881.zip

This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.

Design File(s):

• xapp492_S6_ConnectivityTRD_Aurora.zip

The non-integer data recovery unit (NI-DRU) presented in this application note is specifically designed for RocketIO™ GTP and GTX transceivers in Virtex®-5 LXT, SXT, TXT, and FXT platforms and consists of look-up tables (LUTs) and flip-flops. The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

Design File(s):

• xapp875.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This application note describes the controller and data capture technique for high-performance DDR2 SDRAM interfaces. This data capture technique uses the Input Serializer/Deserializer (ISERDES) and Output Double Data Rate (ODDR) features available in every Virtex®-5 I/O.

This application note discusses the Serial Peripheral Interface (SPI) configuration mode introduced in the Virtex®-5 and Spartan®-3E FPGA families. The ISE® Design Suite with iMPACT in-system programming solution with Xilinx cables for prototype designs is also described.

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/Os in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses parasitic leakage current behavior.

This application note describes three FPGA configuration modes using Flash PROMS.

Design File(s):

• xapp978.zip

This application note presents a Verilog reference design that has been simulated, synthesized, and verified on hardware using Virtex®-6 FPGAs and QDR II SRAM two-word burst devices.

This application note describes a method for bypassing the AC coupling in Virtex™-II Pro X devices. Doing so allows use of the 10 Gb/s RocketIO™ Multi-Gigabit Transceiver (MGT) in DC-coupled over-sampling applications.

Design File(s):

• xapp776.zip

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan®-6 FPGAs.

This application note describes a PRBS generator/checker circuit where the generator polynomial, the parallelism level, and the functionality (generator or checker) are programmable via attributes.

Design File(s):

• xapp884.zip

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Virtex®-6 FPGA mixed-mode clock manager (MMCM) through its dynamic reconfiguration port.

Design File(s):

• xapp878.zip

This application note describes how to interface a Texas Instruments analog-to-digital converter (ADC) with serial low-voltage differential signaling (LVDS) outputs to Virtex®-4 or Virtex-5 FPGAs, utilizing the dedicated deserializer functions of both FPGA families.

Design File(s):

• xapp866.zip

This document describes how to implement triple-rate SDI interfaces using Spartan®-6 FPGAs.

Design File(s):

• xapp1076_S6GTP_TripleRateSDI.zip

This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software.

Design File(s):

• xapp1151_Param_CAM.zip

This application note describes a data integrity controller for partial reconfiguration (PRC) that can be included in any partially reconfigurable FPGA design to process partial bitstreams for data integrity.

Design File(s):

• xapp887_PRC_EPRC.zip

This application note describes how to use the lwIP library to add networking capability to an embedded system. In particular, lwIP is utilized to develop these applications: echo server, Web server, TFTP server and receive and transmit throughput tests.

Design File(s):

• Design files for XAPP1026

The triple-rate serial digital interface, which supports the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards, is widely used in professional broadcast video equipment. This document describes how to implement triple-rate SDI interfaces with GTX transceivers in Virtex®-6 FPGAs.

Design File(s):

• xapp1075.zip

This Application Note describes a set of reference designs that can transmit and receive DVI or HDMI data streams up to 750 Mb/s using the native TMDS I/O featured by Spartan®-3A FPGAs.

Design File(s):

• xapp460.zip

This document provides step-by-step instructions for migrating designs containing instances of either the legacy Dual Port Block Memory and Single Port Block Memory LogiCORE™ IP cores or older versions of the LogiCORE IP Block Memory Generator core.

Design File(s):

• xapp917.zip

Flexible CAMs (Content Addressable Memory) are implemented in Virtex™ devices by taking advantage of the reprogrammability of the basic LUT as a Shift Register or a SelectRAM™ memory and the fast carry logic chain. Although CAMs are also feasible in Spartan™ and XC4000X™ devices, this application note concentrates on Virtex devices.

This application note and reference design gives examples of a typical spread-spectrum clock for video applications using the Spartan®-6 FPGA DCM_CLKGEN primitive. DCM_CLKGEN can be used for fixed spread-spectrum generation without any logic or in a soft spread-spectrum solution using a state machine.

Design File(s):

• xapp1065.zip

This application note describes the methodology for building a Fast PCIe® Configuration (FPC) module using a two-step configuration approach. A reference design is available to help designers quick-launch a PlanAhead™ software partial reconfiguration project.

Design File(s):

• xapp883_Fast_Config_PCIe.zip

The USR_ACCESS register, present in the Virtex®-5, Virtex-6, and all 7 series FPGAs, provides the ability to embed version information into a 32-bit fabric-accessible register at the bitstream generation phase, allowing for the best balance of flexibility for the user with minimal impact to the design and implementation time.

Spartan™ FPGAs are an exciting alternative for implementing digital designs that, previously, would have employed ASIC technology. Pre-existing ASIC intellectual property can be adapted for use with Spartan devices by following a straightforward procedure. Each step of the procedure is explained in detail. Guidelines show how an ASIC design, in the form of an RTL-level HDL file, can be revised to take full advantage of the Spartan series capabilities, thereby achieving efficient, high-performance implementations.

This application note discusses the enormous strides made by Spartan™ series FPGAs in terms of density and performance and how it should be viewed as the Gate Array replacement. The Spartan device family offers many of the features that are desired by Gate Array designers with the major advantage of programmability, which can prove to be the key factor in the success of the product.

This application note describes the implementation of a DisplayPort™ source core and policy maker reference design targeted for the Spartan®-6 FPGA Consumer Video Kit (CVK).

Design File(s):

• xapp493_DisplayPort_SPM.zip

This application note describes the implementation of a DisplayPort&trade sink core and policy maker reference design targeted for the Spartan®-6 FPGA Consumer Video Kit (CVK).

Design File(s):

• xapp593_DisplayPort_Sink.zip

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

This application note discusses how to design and implement a Bus Master design using Xilinx® Endpoint PCI Express® solutions. A performance demonstration reference design using Bus Mastering is included with this application note. The reference design can be used to gauge achievable performance in various systems and act as a starting point for an application-specific Bus Master Direct Memory Access (DMA). The reference design includes all files necessary to target the Integrated Blocks for PCI Express on the Virtex®-6 and Spartan®-6 FPGAs, the Endpoint Block Plus Wrapper Core for PCI Express using the Virtex-5 FPGA Integrated Block for PCI Express, and the Endpoint PIPE for PCI Express targeting the Xilinx Spartan®-3 family of devices.

Design File(s):

• xapp1052.zip

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan®-6 FPGA Phase Locked Loop (PLL) through its Dynamic Reconfiguration Port (DRP).

Design File(s):

• xapp879.zip

The FIFO Generator Migration Guide provides step-by-step instructions for migrating existing designs containing instances of legacy FIFO cores (Synchronous FIFO v5.x and Asynchronous FIFO v6.x) to the latest version of the FIFO Generator. This document contains information about the AXI4 version of the core.

Design File(s):

• xapp992.zip

This application note provides anti-tamper (AT) guidance and practical examples to help the FPGA designer protect the intellectual property (IP) and sensitive data that might exist in an FPGA-enabled system.

This application note includes a method for sharing an internal configuration access port (ICAP) between the user design and the soft error mitigation (SEM) controller in the Spartan®-6 and Virtex®-6 devices.

Design File(s):

• xapp517_DualUse_ICAP_SEM.zip

The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems.

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the 7 series FPGAs mixed-mode clock manager (MMCM). Similarly, the phase-locked loop (PLL) can be changed through the dynamic reconfiguration port (DRP). An explanation of the behavior of the internal DRP control registers is accompanied by a reference design that uses a state machine to drive the DRP, which ensures the registers are controlled in the correct sequence.

Design File(s):

• xapp888.zip

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core.

Design File(s):

• xapp740_axi_video.zip

The Virtex™-5QV device combines high logic density and radiation-hardened by design (RHBD) features with 12-transistor (12T) configuration memory cells. The result is the fastest and largest FPGA available for high-reliability space applications.

Design File(s):

• xapp588.zip

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

MP3 portable players are the trend in music-listening technology. These players do not include any mechanical movements, thereby making them ideal for listening to music during any type of activity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music in a lot less space than current CD technology. Software is readily available to create MP3 files from an existing CD, and the user can then download these files into a portable MP3 player to be enjoyed in almost any environment.

This application note shows how a Xilinx® CoolRunner™-II CPLD can be used as a simple logical switch that can quickly and reliably select between different MPEG video sources.

Design File(s):

• xapp944_source.zip.zip

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This Application Note describes a set of reference designs that can transmit and receive DVI or HDMI data streams up to 750 Mb/s using the native TMDS I/O featured by Spartan®-3A FPGAs.

Design File(s):

• xapp460.zip

This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.

Design File(s):

• xapp953.zip

This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD.

This application note describes the implementation of a YCrCb color space to an RGB Color space conversion circuit necessary in many video designs.

Design File(s):

• xapp931.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

Design File(s):

• xapp932.zip

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan®-6 FPGAs.

This Application Note describes a set of reference designs that can transmit and receive DVI or HDMI data streams up to 750 Mb/s using the native TMDS I/O featured by Spartan®-3A FPGAs.

Design File(s):

• xapp460.zip

This book-length compendium of Virtex®-II Pro and Virtex-4 audio and video connectivity solutions for the broadcast industry contains the latest updated revisions of previously published serial video application notes as well as new designs not previously released. See the Preface for a list of the original application note numbers this volume replaces.

Design File(s):

• xapp514.zip

This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices.

This document presents design techniques and reference circuits that power Virtex™-4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

This application note describes the implementation of a Virtex™-4 RocketIO bit-error rate tester (XBERT) reference design. The XBERT reference design generates and verifies non-encoded or 8B/10B-encoded high-speed serial data on one or multiple point-to-point links between Virtex-4 RocketIO Multi-Gigabit Transceiver (MGT) ports embedded within a single Virtex-4 FPGA.

Design File(s):

• xapp713.zip

This application note describes the implementation details of a bridge between a 133-MHz, 64-bit PCI-X interface and a 128 MB Double Data Rate (DDR), Small-Outline Dual Inline Memory Module (SODIMM) interface for Virtex™-4 devices. The reference design is capable of reading and writing up to four KB bursts of 64-bit data at 133 MHz.

Design File(s):

• xapp708.zip

This is a reference design for the Spartan™-3E Display Development Kit to assist in developing display panel products. The display solution FPGA design consists of a Video Input interface, Color Temperature Correction, Precise Gamma Correction, Image Dithering Engine, and an output interface.

Design File(s):

• xapp928.zip

Using CoolRunner™-II CPLDs with standard chipsets.

Uses CoolRunner™-II to control dot matrix LCD module. Includes design file.

Design File(s):

• xapp904_code.zip

This reference system tests the operation of the OPB CAN core in loopback mode.

Design File(s):

• xapp913.zip

This application note describes how to use Spartan®-3E FPGAs to implement various serial digital video interfaces commonly used in the professional video broadcast industry.

Design File(s):

• xapp1015.zip

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp485.zip

The OPB USB 2.0 Device core performs the functionality of a USB high speed device and is compliant with the USB 2.0 Specification.

Design File(s):

• xapp997.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp486.zip
• xapp486.zip

This application note is a collection of audio and video connectivity solutions for the broadcast industry. It describes how to use Virtex®-5 FPGAs to implement serial digital video and audio interfaces commonly used in the professional video broadcast industry. The associated reference designs support many video rates and standards, and provide for embedded audio.

Design File(s):

• xapp1014.zip

This Application Note describes a set of reference designs that can transmit and receive DVI or HDMI data streams up to 750 Mb/s using the native TMDS I/O featured by Spartan®-3A FPGAs.

Design File(s):

• xapp460.zip

This application note and reference design gives examples of a typical spread-spectrum clock for video applications using the Spartan®-6 FPGA DCM_CLKGEN