00001 /* $Id: */ 00002 /****************************************************************************** 00003 * (c) Copyright 2009 Xilinx, Inc. All rights reserved. 00004 * 00005 * This file contains confidential and proprietary information 00006 * of Xilinx, Inc. and is protected under U.S. and 00007 * international copyright and other intellectual property 00008 * laws. 00009 * 00010 * DISCLAIMER 00011 * This disclaimer is not a license and does not grant any 00012 * rights to the materials distributed herewith. Except as 00013 * otherwise provided in a valid license issued to you by 00014 * Xilinx, and to the maximum extent permitted by applicable 00015 * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 * (2) Xilinx shall not be liable (whether in contract or tort, 00021 * including negligence, or under any other theory of 00022 * liability) for any loss or damage of any kind or nature 00023 * related to, arising under or in connection with these 00024 * materials, including for any direct, or any indirect, 00025 * special, incidental, or consequential loss or damage 00026 * (including loss of data, profits, goodwill, or any type of 00027 * loss or damage suffered as a result of any action brought 00028 * by a third party) even if such damage or loss was 00029 * reasonably foreseeable or Xilinx had been advised of the 00030 * possibility of the same. 00031 * 00032 * CRITICAL APPLICATIONS 00033 * Xilinx products are not designed or intended to be fail- 00034 * safe, or for use in any application requiring fail-safe 00035 * performance, such as life-support or safety devices or 00036 * systems, Class III medical devices, nuclear facilities, 00037 * applications related to the deployment of airbags, or any 00038 * other applications that could lead to death, personal 00039 * injury, or severe property or environmental damage 00040 * (individually and collectively, "Critical 00041 * Applications"). Customer assumes the sole risk and 00042 * liability of any use of Xilinx products in Critical 00043 * Applications, subject only to applicable laws and 00044 * regulations governing limitations on product liability. 00045 * 00046 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 * PART OF THIS FILE AT ALL TIMES. 00048 * 00049 * All rights reserved. 00050 * 00051 ******************************************************************************/ 00052 /*****************************************************************************/ 00053 /** 00054 * 00055 * @file xtimebase_hw.h 00056 * 00057 * This header file contains identifiers and register-level driver functions (or 00058 * macros) that can be used to access the Xilinx MVI Video TimeBase device. 00059 * 00060 * For more information about the operation of this device, see the hardware 00061 * specification and documentation in the higher level driver xtimebase.h source 00062 * code file. 00063 * 00064 * <pre> 00065 * MODIFICATION HISTORY: 00066 * 00067 * Ver Who Date Changes 00068 * ----- ---- -------- ----------------------------------------------- 00069 * 1.00a xd 08/05/08 First release 00070 * 1.01a xd 07/23/10 Added GIER; Added more h/w generic info into 00071 * xparameters.h; Feed callbacks with pending 00072 * interrupt info. Added Doxygen & Version support 00073 * </pre> 00074 * 00075 ******************************************************************************/ 00076 00077 #ifndef XTIMEBASE_HW_H /* prevent circular inclusions */ 00078 #define XTIMEBASE_HW_H /* by using protection macros */ 00079 00080 #ifdef __cplusplus 00081 extern "C" { 00082 #endif 00083 00084 /***************************** Include Files *********************************/ 00085 00086 #include "xio.h" 00087 00088 /************************** Constant Definitions *****************************/ 00089 00090 /** @name Device Register Offsets 00091 * @{ 00092 */ 00093 #define XTB_CTL 0x000 /**< Control */ 00094 00095 #define XTB_GH0 0x004 /**< Generator Horizontal Register 0 */ 00096 #define XTB_GH1 0x008 /**< Generator Horizontal Register 1 */ 00097 #define XTB_GH2 0x00C /**< Generator Horizontal Register 2 */ 00098 #define XTB_GV0 0x010 /**< Generator Vertical Register 0 */ 00099 #define XTB_GV1 0x014 /**< Generator Vertical Register 1 */ 00100 #define XTB_GV2 0x018 /**< Generator Vertical Register 2 */ 00101 #define XTB_GV3 0x01C /**< Generator Vertical Register 3 */ 00102 #define XTB_GV4 0x020 /**< Generator Vertical Register 4 */ 00103 #define XTB_GV5 0x024 /**< Generator Vertical Register 5 */ 00104 00105 #define XTB_DS 0x028 /**< Detector Status Register */ 00106 00107 #define XTB_DH0 0x02C /**< Detector Horizontal Register 0 */ 00108 #define XTB_DH1 0x030 /**< Detector Horizontal Register 1 */ 00109 #define XTB_DH2 0x034 /**< Detector Horizontal Register 2 */ 00110 #define XTB_DV0 0x038 /**< Detector Vertical Register 0 */ 00111 #define XTB_DV1 0x03C /**< Detector Vertical Register 1 */ 00112 #define XTB_DV2 0x040 /**< Detector Vertical Register 2 */ 00113 #define XTB_DV3 0x044 /**< Detector Vertical Register 3 */ 00114 #define XTB_DV4 0x048 /**< Detector Vertical Register 4 */ 00115 #define XTB_DV5 0x04C /**< Detector Vertical Register 5 */ 00116 00117 #define XTB_FS00 0x050 /**< Frame Sync 00 Config Register */ 00118 #define XTB_FS01 0x054 /**< Frame Sync 01 Config Register */ 00119 #define XTB_FS02 0x058 /**< Frame Sync 02 Config Register */ 00120 #define XTB_FS03 0x05C /**< Frame Sync 03 Config Register */ 00121 #define XTB_FS04 0x060 /**< Frame Sync 04 Config Register */ 00122 #define XTB_FS05 0x064 /**< Frame Sync 05 Config Register */ 00123 #define XTB_FS06 0x068 /**< Frame Sync 06 Config Register */ 00124 #define XTB_FS07 0x06C /**< Frame Sync 07 Config Register */ 00125 #define XTB_FS08 0x070 /**< Frame Sync 08 Config Register */ 00126 #define XTB_FS09 0x074 /**< Frame Sync 09 Config Register */ 00127 #define XTB_FS10 0x078 /**< Frame Sync 10 Config Register */ 00128 #define XTB_FS11 0x07C /**< Frame Sync 11 Config Register */ 00129 #define XTB_FS12 0x080 /**< Frame Sync 12 Config Register */ 00130 #define XTB_FS13 0x084 /**< Frame Sync 13 Config Register */ 00131 #define XTB_FS14 0x088 /**< Frame Sync 14 Config Register */ 00132 #define XTB_FS15 0x08C /**< Frame Sync 15 Config Register */ 00133 00134 #define XTB_GGD 0x090 /**< Generator Global Delay register */ 00135 00136 #define XTB_VER 0x0F0 /**< Version Register */ 00137 #define XTB_RESET 0x100 /**< Reset Register */ 00138 #define XTB_GIER 0x21C /**< Global Interrupt Enable Register */ 00139 #define XTB_ISR 0x220 /**< Interrupt Status Register */ 00140 #define XTB_IER 0x228 /**< Interrupt Enable Register */ 00141 /*@}*/ 00142 00143 /** @name Control Register bit definition 00144 * @{ 00145 */ 00146 #define XTB_CTL_ACP_MASK 0x04000000 /**< Active Chroma Output Polarity*/ 00147 #define XTB_CTL_AVP_MASK 0x02000000 /**< Active Video Output Polarity */ 00148 #define XTB_CTL_FIP_MASK 0x01000000 /**< Field ID Output Polarity */ 00149 #define XTB_CTL_VBP_MASK 0x00800000 /**< Vertical Blank Output Polarity 00150 */ 00151 #define XTB_CTL_VSP_MASK 0x00400000 /**< Vertical Sync Output Polarity 00152 */ 00153 #define XTB_CTL_HBP_MASK 0x00200000 /**< Horizontal Blank Output 00154 * Polarity */ 00155 #define XTB_CTL_HSP_MASK 0x00100000 /**< Horizontal Sync Output Polarity 00156 */ 00157 #define XTB_CTL_ALLP_MASK 0x07F00000 /**< Bit mask for all polarity bits 00158 */ 00159 #define XTB_CTL_VCSS_MASK 0x00040000 /**< Start of Active Chroma Register 00160 * Source Select */ 00161 #define XTB_CTL_VASS_MASK 0x00020000 /**< Vertical Active Video Start 00162 * Register Source Select */ 00163 #define XTB_CTL_VBSS_MASK 0x00010000 /**< Vertical Back Porch Start 00164 * Register Source Select */ 00165 #define XTB_CTL_VSSS_MASK 0x00008000 /**< Vertical Sync Start Register 00166 * Source Select */ 00167 #define XTB_CTL_VFSS_MASK 0x00004000 /**< Vertical Front Porch Start 00168 * Register Source Select */ 00169 #define XTB_CTL_VTSS_MASK 0x00002000 /**< Vertical Total Register Source 00170 * Select */ 00171 #define XTB_CTL_HASS_MASK 0x00001000 /**< Horizontal Active Video Start 00172 * Register Source Select */ 00173 #define XTB_CTL_HBSS_MASK 0x00000800 /**< Horizontal Back Porch Start 00174 * Register Source Select */ 00175 #define XTB_CTL_HSSS_MASK 0x00000400 /**< Horizontal Sync Start Register 00176 * Source Select */ 00177 #define XTB_CTL_HFSS_MASK 0x00000200 /**< Horizontal Front Porch Start 00178 * Register Source Select */ 00179 #define XTB_CTL_HTSS_MASK 0x00000100 /**< Horizontal Total Register 00180 * Source Select */ 00181 #define XTB_CTL_ALLSS_MASK 0x0007FF00 /**< Bit mask for all source select 00182 */ 00183 #define XTB_CTL_GACS_MASK 0x00000010 /**< Generator Active Chroma Skip */ 00184 #define XTB_CTL_LP_MASK 0x00000008 /**< Lock Polarity */ 00185 #define XTB_CTL_DE_MASK 0x00000002 /**< Timebase Detector Enable */ 00186 #define XTB_CTL_GE_MASK 0x00000001 /**< Timebase Generator Enable */ 00187 /*@}*/ 00188 00189 /** @name TimeBase Generator Horizontal 0 00190 * @{ 00191 */ 00192 #define XTB_GH0_FPSTART_MASK 0x0FFF0000 /**< Horizontal Front Porch Start 00193 * Cycle Count */ 00194 #define XTB_GH0_FPSTART_SHIFT 16 /**< Bit shift for Horizontal 00195 * Front Porch Start Cycle 00196 * Count */ 00197 #define XTB_GH0_TOTAL_MASK 0x00000FFF /**< Total clock cycles per Line 00198 */ 00199 /*@}*/ 00200 00201 /** @name TimeBase Generator Horizontal 1 00202 * @{ 00203 */ 00204 #define XTB_GH1_BPSTART_MASK 0x0FFF0000 /**< Horizontal Back Porch Start 00205 * Cycle Count */ 00206 #define XTB_GH1_BPSTART_SHIFT 16 /**< Bit shift for Horizontal Back 00207 * Porch Start Cycle Count */ 00208 #define XTB_GH1_SYNCSTART_MASK 0x00000FFF /**< Horizontal Sync Start Cycle 00209 * Count */ 00210 /*@}*/ 00211 00212 /** @name TimeBase Generator Horizontal 2 00213 * @{ 00214 */ 00215 #define XTB_GH2_ACTIVESTART_MASK 0x00000FFF /**< Horizontal Active Video Start 00216 * Cycle Count */ 00217 /*@}*/ 00218 00219 /** @name TimeBase Generator Vertical 0 (Field 0) 00220 * @{ 00221 */ 00222 #define XTB_GV0_FPSTART_MASK 0x0FFF0000 /**< Vertical Front Porch Start 00223 * Cycle Count */ 00224 #define XTB_GV0_FPSTART_SHIFT 16 /**< Bit shift for Vertical Front 00225 * Porch Start Cycle Count */ 00226 #define XTB_GV0_TOTAL_MASK 0x00000FFF /**< Total lines per Frame */ 00227 /*@}*/ 00228 00229 /** @name TimeBase Generator Vertical 1 (Field 0) 00230 * @{ 00231 */ 00232 #define XTB_GV1_BPSTART_MASK 0x0FFF0000 /**< Vertical Back Porch Start 00233 * Cycle Count */ 00234 #define XTB_GV1_BPSTART_SHIFT 16 /**< Bit shift for Vertical Back 00235 * Porch Start Cycle Count */ 00236 #define XTB_GV1_SYNCSTART_MASK 0x00000FFF /**< Vertical Sync Start Cycle 00237 * Count */ 00238 /*@}*/ 00239 00240 /** @name TimeBase Generator Vertical 2 (Field 0) 00241 * @{ 00242 */ 00243 #define XTB_GV2_CHROMASTART_MASK 0x0FFF0000 /**< Active Chroma Start Line 00244 * Count */ 00245 #define XTB_GV2_CHROMASTART_SHIFT 16 /**< Bit shift for Active Chroma 00246 * Start Line Count */ 00247 #define XTB_GV2_ACTIVESTART_MASK 0x00000FFF /**< Vertical Active Video Start 00248 * Cycle Count */ 00249 /*@}*/ 00250 00251 /** @name TimeBase Generator Vertical 3 (Field 1) 00252 * @{ 00253 */ 00254 #define XTB_GV3_FPSTART_MASK 0x0FFF0000 /**< Vertical Front Porch Start 00255 * Cycle Count */ 00256 #define XTB_GV3_FPSTART_SHIFT 16 /**< Bit shift for Vertical Front 00257 * Porch Start Cycle Count */ 00258 #define XTB_GV3_TOTAL_MASK 0x00000FFF /**< Total lines per Frame */ 00259 /*@}*/ 00260 00261 /** @name TimeBase Generator Vertical 4 (Field 1) 00262 * @{ 00263 */ 00264 #define XTB_GV4_BPSTART_MASK 0x0FFF0000 /**< Vertical Back Porch Start 00265 * Cycle Count */ 00266 #define XTB_GV4_BPSTART_SHIFT 16 /**< Bit shift for Vertical Back 00267 * Porch Start Cycle Count */ 00268 #define XTB_GV4_SYNCSTART_MASK 0x00000FFF /**< Vertical Sync Start Cycle 00269 * Count */ 00270 /*@}*/ 00271 00272 /** @name TimeBase Generator Vertical 5 (Field 1) 00273 * @{ 00274 */ 00275 #define XTB_GV5_CHROMASTART_MASK 0x0FFF0000 /**< Active Chroma Start Line 00276 * Count */ 00277 #define XTB_GV5_CHROMASTART_SHIFT 16 /**< Bit shift for Active Chroma 00278 * Start Line Count */ 00279 #define XTB_GV5_ACTIVESTART_MASK 0x00000FFF /**< Vertical Active Video Start 00280 * Cycle Count */ 00281 /*@}*/ 00282 00283 /** @name TimeBase Detector Status 00284 * @{ 00285 */ 00286 #define XTB_DS_AC_POL_MASK 0x04000000 /**< Active Chroma Output Polarity 00287 */ 00288 #define XTB_DS_AV_POL_MASK 0x02000000 /**< Active Video Output Polarity 00289 */ 00290 #define XTB_DS_FID_POL_MASK 0x01000000 /**< Field ID Output Polarity */ 00291 #define XTB_DS_VBLANK_POL_MASK 0x00800000 /**< Vertical Blank Output 00292 * Polarity */ 00293 #define XTB_DS_VSYNC_POL_MASK 0x00400000 /**< Vertical Sync Output Polarity 00294 */ 00295 #define XTB_DS_HBLANK_POL_MASK 0x00200000 /**< Horizontal Blank Output 00296 * Polarity */ 00297 #define XTB_DS_HSYNC_POL_MASK 0x00100000 /**< Horizontal Sync Output 00298 * Polarity */ 00299 #define XTB_DS_ACSKIP_MASK 0x00000010 /**< Detector Active Chroma Skip 00300 */ 00301 /*@}*/ 00302 00303 /** @name TimeBase Detector Horizontal 0 00304 * @{ 00305 */ 00306 #define XTB_DH0_FPSTART_MASK 0x0FFF0000 /**< Detected Horizontal Front 00307 * Porch Start Cycle Count */ 00308 #define XTB_DH0_FPSTART_SHIFT 16 /**< Bit shift for Detected 00309 * Horizontal Front Porch Start 00310 * Cycle Count */ 00311 #define XTB_DH0_TOTAL_MASK 0x00000FFF /**< Detected Total clock cycles 00312 * per Line */ 00313 /*@}*/ 00314 00315 /** @name TimeBase Detector Horizontal 1 00316 * @{ 00317 */ 00318 #define XTB_DH1_BPSTART_MASK 0x0FFF0000 /**< Detected Horizontal Back 00319 * Porch Start Cycle Count */ 00320 #define XTB_DH1_BPSTART_SHIFT 16 /**< Bit shift for Detected 00321 * Horizontal Back Porch Start 00322 * Cycle Count */ 00323 #define XTB_DH1_SYNCSTART_MASK 0x00000FFF /**< Detected Horizontal Sync 00324 * Start Cycle Count */ 00325 /*@}*/ 00326 00327 /** @name TimeBase Detector Horizontal 2 00328 * @{ 00329 */ 00330 #define XTB_DH2_ACTIVESTART_MASK 0x00000FFF /**< Detected Horizontal Active 00331 * Video Start Cycle Count */ 00332 /*@}*/ 00333 00334 /** @name TimeBase Detector Vertical 0 (Field 0) 00335 * @{ 00336 */ 00337 #define XTB_DV0_FPSTART_MASK 0x0FFF0000 /**< Detected Vertical Front Porch 00338 * Start Cycle Count */ 00339 #define XTB_DV0_FPSTART_SHIFT 16 /**< Bit shift for Detected 00340 * Vertical Front Porch Start 00341 * Cycle Count */ 00342 #define XTB_DV0_TOTAL_MASK 0x00000FFF /**< Detected Total lines per 00343 * Frame */ 00344 /*@}*/ 00345 00346 /** @name TimeBase Detector Vertical 1 (Field 0) 00347 * @{ 00348 */ 00349 #define XTB_DV1_BPSTART_MASK 0x0FFF0000 /**< Detected Vertical Back Porch 00350 * Start Cycle Count */ 00351 #define XTB_DV1_BPSTART_SHIFT 16 /**< Bit shift for Detected 00352 * Vertical Back Porch Start 00353 * Cycle Count */ 00354 #define XTB_DV1_SYNCSTART_MASK 0x00000FFF /**< Detected Vertical Sync Start 00355 * Cycle Count */ 00356 /*@}*/ 00357 00358 /** @name TimeBase Detector Vertical 2 (Field 0) 00359 * @{ 00360 */ 00361 #define XTB_DV2_CHROMASTART_MASK 0x0FFF0000 /**< Detected Active Chroma Start 00362 * Line Count */ 00363 #define XTB_DV2_CHROMASTART_SHIFT 16 /**< Bit shift for Detected Active 00364 * Chroma Start Line Count */ 00365 #define XTB_DV2_ACTIVESTART_MASK 0x00000FFF /**< Detected Vertical Active 00366 * Video Start Cycle Count */ 00367 /*@}*/ 00368 00369 /** @name TimeBase Detector Vertical 3 (Field 1) 00370 * @{ 00371 */ 00372 #define XTB_DV3_FPSTART_MASK 0x0FFF0000 /**< Detected Vertical Front Porch 00373 * Start Cycle Count */ 00374 #define XTB_DV3_FPSTART_SHIFT 16 /**< Bit shift for Detected 00375 * Vertical Front Porch Start 00376 * Cycle Count */ 00377 #define XTB_DV3_TOTAL_MASK 0x00000FFF /**< Detected Total lines per 00378 * Frame */ 00379 /*@}*/ 00380 00381 /** @name TimeBase Detector Vertical 4 (Field 1) 00382 * @{ 00383 */ 00384 #define XTB_DV4_BPSTART_MASK 0x0FFF0000 /**< Detected Vertical Back Porch 00385 * Start Cycle Count */ 00386 #define XTB_DV4_BPSTART_SHIFT 16 /**< Bit shift for Detected 00387 * Vertical Back Porch Start 00388 * Cycle Count */ 00389 #define XTB_DV4_SYNCSTART_MASK 0x00000FFF /**< Detected Vertical Sync Start 00390 * Cycle Count */ 00391 /*@}*/ 00392 00393 /** @name TimeBase Detector Vertical 5 (Field 1) 00394 * @{ 00395 */ 00396 #define XTB_DV5_CHROMASTART_MASK 0x0FFF0000 /**< Detected Active Chroma Start 00397 * Line Count */ 00398 #define XTB_DV5_CHROMASTART_SHIFT 16 /**< Bit shift for Detected Active 00399 * Chroma Start Line Count */ 00400 #define XTB_DV5_ACTIVESTART_MASK 0x00000FFF /**< Detected Vertical Active 00401 * Video Start Cycle Count */ 00402 /*@}*/ 00403 00404 /** @name Timebase Generator Global Delay 00405 * @{ 00406 */ 00407 #define XTB_GGD_VDELAY_MASK 0x0FFF0000 /**< Total lines per frame to delay 00408 * generator output */ 00409 #define XTB_GGD_VDELAY_SHIFT 16 /**< Bit shift for the total 00410 * lines */ 00411 #define XTB_GGD_HDELAY_MASK 0x00000FFF /**< Total clock cycles per line to 00412 * delay generator output */ 00413 /*@}*/ 00414 00415 00416 /** @name Timebase Frame Sync 00 --- 15 00417 * @{ 00418 */ 00419 #define XTB_FSXX_VSTART_MASK 0x0FFF0000 /**< Vertical line count during 00420 * which current Frame Sync is 00421 * active */ 00422 #define XTB_FSXX_VSTART_SHIFT 16 /**< Bit shift for the vertical 00423 * line count */ 00424 #define XTB_FSXX_HSTART_MASK 0x00000FFF /**< Horizontal cycle count during 00425 * which current Frame Sync is 00426 * active */ 00427 /*@}*/ 00428 00429 /** @name Reset Register bit definition 00430 * @{ 00431 */ 00432 #define XTB_RESET_RESET_MASK 0x0000000A /**< Software Reset */ 00433 /*@}*/ 00434 00435 /** @name Version Register bit definition 00436 * @{ 00437 */ 00438 #define XTB_VER_MAJOR_MASK 0xF0000000 /**< Major Version*/ 00439 #define XTB_VER_MAJOR_SHIFT 28 /**< Major Version Bit Shift*/ 00440 #define XTB_VER_MINOR_MASK 0x0FF00000 /**< Minor Version */ 00441 #define XTB_VER_MINOR_SHIFT 20 /**< Minor Version Bit Shift*/ 00442 #define XTB_VER_REV_MASK 0x000F0000 /**< Revision Version */ 00443 #define XTB_VER_REV_SHIFT 16 /**< Revision Bit Shift*/ 00444 /*@}*/ 00445 00446 /** @name Global Interrupt Enable Register bit definition 00447 * @{ 00448 */ 00449 #define XTB_GIER_GIE_MASK 0x80000000 /**< Global interrupt enable */ 00450 /*@}*/ 00451 00452 /** @name Interrupt Status/Enable Register bit definition 00453 * @{ 00454 */ 00455 #define XTB_IXR_FSYNC15_MASK 0x80000000 /**< Frame Sync Interrupt 15 */ 00456 #define XTB_IXR_FSYNC14_MASK 0x40000000 /**< Frame Sync Interrupt 14 */ 00457 #define XTB_IXR_FSYNC13_MASK 0x20000000 /**< Frame Sync Interrupt 13 */ 00458 #define XTB_IXR_FSYNC12_MASK 0x10000000 /**< Frame Sync Interrupt 12 */ 00459 #define XTB_IXR_FSYNC11_MASK 0x08000000 /**< Frame Sync Interrupt 11 */ 00460 #define XTB_IXR_FSYNC10_MASK 0x04000000 /**< Frame Sync Interrupt 10 */ 00461 #define XTB_IXR_FSYNC09_MASK 0x02000000 /**< Frame Sync Interrupt 09 */ 00462 #define XTB_IXR_FSYNC08_MASK 0x01000000 /**< Frame Sync Interrupt 08 */ 00463 #define XTB_IXR_FSYNC07_MASK 0x00800000 /**< Frame Sync Interrupt 07 */ 00464 #define XTB_IXR_FSYNC06_MASK 0x00400000 /**< Frame Sync Interrupt 06 */ 00465 #define XTB_IXR_FSYNC05_MASK 0x00200000 /**< Frame Sync Interrupt 05 */ 00466 #define XTB_IXR_FSYNC04_MASK 0x00100000 /**< Frame Sync Interrupt 04 */ 00467 #define XTB_IXR_FSYNC03_MASK 0x00080000 /**< Frame Sync Interrupt 03 */ 00468 #define XTB_IXR_FSYNC02_MASK 0x00040000 /**< Frame Sync Interrupt 02 */ 00469 #define XTB_IXR_FSYNC01_MASK 0x00020000 /**< Frame Sync Interrupt 01 */ 00470 #define XTB_IXR_FSYNC00_MASK 0x00010000 /**< Frame Sync Interrupt 00 */ 00471 #define XTB_IXR_FSYNCALL_MASK 0xFFFF0000 /**< All Frame Sync Interrupt 0-15*/ 00472 00473 #define XTB_IXR_G_AV_MASK 0x00002000 /**< Generator Active Video Intr */ 00474 #define XTB_IXR_G_VBLANK_MASK 0x00001000 /**< Generator VBLANK Interrupt */ 00475 #define XTB_IXR_G_ALL_MASK 0x00003000 /**< All Generator interrupts */ 00476 00477 #define XTB_IXR_D_AV_MASK 0x00000200 /**< Detector Active Video Intr */ 00478 #define XTB_IXR_D_VBLANK_MASK 0x00000100 /**< Detector VBLANK Interrupt */ 00479 #define XTB_IXR_D_ALL_MASK 0x00000300 /**< All Detector interrupts */ 00480 00481 #define XTB_IXR_AL_MASK 0x00000080 /**< All lock */ 00482 #define XTB_IXR_ACL_MASK 0x00000040 /**< Active Chroma signal lock */ 00483 #define XTB_IXR_AVL_MASK 0x00000020 /**< Active Video Signal Lock */ 00484 #define XTB_IXR_FIL_MASK 0x00000010 /**< Field ID Signal Lock */ 00485 #define XTB_IXR_VBL_MASK 0x00000008 /**< Vertical Blank Signal Lock */ 00486 #define XTB_IXR_VSL_MASK 0x00000004 /**< Vertical Sync Signal Lock */ 00487 #define XTB_IXR_HBL_MASK 0x00000002 /**< Horizontal Blank Signal Lock */ 00488 #define XTB_IXR_HSL_MASK 0x00000001 /**< Horizontal Sync Signal Lock */ 00489 #define XTB_IXR_LOCKALL_MASK 0x000000FF /**< All Signal Lock interrupt */ 00490 #define XTB_IXR_ALLINTR_MASK (XTB_IXR_FSYNCALL_MASK | XTB_IXR_G_ALL_MASK | \ 00491 XTB_IXR_D_ALL_MASK | \ 00492 XTB_IXR_LOCKALL_MASK) /**< Mask for all 00493 * interrupts 00494 */ 00495 /*@}*/ 00496 00497 /**************************** Type Definitions *******************************/ 00498 00499 00500 /***************** Macros (Inline Functions) Definitions *********************/ 00501 00502 /** @name Register Access Macro Definition 00503 * @{ 00504 */ 00505 #define XTimeBase_In32 XIo_In32 00506 #define XTimeBase_Out32 XIo_Out32 00507 00508 /*****************************************************************************/ 00509 /** 00510 * 00511 * Read the given register. 00512 * 00513 * @param BaseAddress is the base address of the device 00514 * @param RegOffset is the register offset to be read 00515 * 00516 * @return The 32-bit value of the register 00517 * 00518 * @note 00519 * C-style signature: 00520 * u32 XTimeBase_ReadReg(u32 BaseAddress, u32 RegOffset) 00521 * 00522 ******************************************************************************/ 00523 #define XTimeBase_ReadReg(BaseAddress, RegOffset) \ 00524 XTimeBase_In32((BaseAddress) + (RegOffset)) 00525 00526 /*****************************************************************************/ 00527 /** 00528 * 00529 * Write the given register. 00530 * 00531 * @param BaseAddress is the base address of the device 00532 * @param RegOffset is the register offset to be written 00533 * @param Data is the 32-bit value to write to the register 00534 * 00535 * @return None. 00536 * 00537 * @note 00538 * C-style signature: 00539 * void XTimeBase_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) 00540 * 00541 ******************************************************************************/ 00542 #define XTimeBase_WriteReg(BaseAddress, RegOffset, Data) \ 00543 XTimeBase_Out32((BaseAddress) + (RegOffset), (Data)) 00544 00545 /*@}*/ 00546 00547 /************************** Function Prototypes ******************************/ 00548 00549 #ifdef __cplusplus 00550 } 00551 #endif 00552 00553 #endif /* end of protection macro */