00001 /* $Id: */ 00002 /****************************************************************************** 00003 -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 00004 -- 00005 -- This file contains confidential and proprietary information 00006 -- of Xilinx, Inc. and is protected under U.S. and 00007 -- international copyright and other intellectual property 00008 -- laws. 00009 -- 00010 -- DISCLAIMER 00011 -- This disclaimer is not a license and does not grant any 00012 -- rights to the materials distributed herewith. Except as 00013 -- otherwise provided in a valid license issued to you by 00014 -- Xilinx, and to the maximum extent permitted by applicable 00015 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00016 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00017 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00018 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00019 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00020 -- (2) Xilinx shall not be liable (whether in contract or tort, 00021 -- including negligence, or under any other theory of 00022 -- liability) for any loss or damage of any kind or nature 00023 -- related to, arising under or in connection with these 00024 -- materials, including for any direct, or any indirect, 00025 -- special, incidental, or consequential loss or damage 00026 -- (including loss of data, profits, goodwill, or any type of 00027 -- loss or damage suffered as a result of any action brought 00028 -- by a third party) even if such damage or loss was 00029 -- reasonably foreseeable or Xilinx had been advised of the 00030 -- possibility of the same. 00031 -- 00032 -- CRITICAL APPLICATIONS 00033 -- Xilinx products are not designed or intended to be fail- 00034 -- safe, or for use in any application requiring fail-safe 00035 -- performance, such as life-support or safety devices or 00036 -- systems, Class III medical devices, nuclear facilities, 00037 -- applications related to the deployment of airbags, or any 00038 -- other applications that could lead to death, personal 00039 -- injury, or severe property or environmental damage 00040 -- (individually and collectively, "Critical 00041 -- Applications"). Customer assumes the sole risk and 00042 -- liability of any use of Xilinx products in Critical 00043 -- Applications, subject only to applicable laws and 00044 -- regulations governing limitations on product liability. 00045 -- 00046 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00047 -- PART OF THIS FILE AT ALL TIMES. 00048 ******************************************************************************/ 00049 /*****************************************************************************/ 00050 /** 00051 * 00052 * @file xvtc_hw.h 00053 * 00054 * This header file contains identifiers and register-level driver functions (or 00055 * macros) that can be used to access the Xilinx MVI VTC device. 00056 * 00057 * For more information about the operation of this device, see the hardware 00058 * specification and documentation in the higher level driver xvtc.h source 00059 * code file. 00060 * 00061 * <pre> 00062 * MODIFICATION HISTORY: 00063 * 00064 * Ver Who Date Changes 00065 * ----- ---- -------- ----------------------------------------------- 00066 * 1.00a xd 08/05/08 First release 00067 * 1.01a xd 07/23/10 Added GIER; Added more h/w generic info into 00068 * xparameters.h; Feed callbacks with pending 00069 * interrupt info. Added Doxygen & Version support 00070 * </pre> 00071 * 00072 ******************************************************************************/ 00073 00074 #ifndef XVTC_HW_H /* prevent circular inclusions */ 00075 #define XVTC_HW_H /* by using protection macros */ 00076 00077 #ifdef __cplusplus 00078 extern "C" { 00079 #endif 00080 00081 /***************************** Include Files *********************************/ 00082 00083 #include "xio.h" 00084 00085 /************************** Constant Definitions *****************************/ 00086 00087 /** @name Device Register Offsets 00088 * @{ 00089 */ 00090 #define XVTC_CTL 0x000 /**< Control */ 00091 00092 #define XVTC_GH0 0x004 /**< Generator Horizontal Register 0 */ 00093 #define XVTC_GH1 0x008 /**< Generator Horizontal Register 1 */ 00094 #define XVTC_GH2 0x00C /**< Generator Horizontal Register 2 */ 00095 #define XVTC_GV0 0x010 /**< Generator Vertical Register 0 */ 00096 #define XVTC_GV1 0x014 /**< Generator Vertical Register 1 */ 00097 #define XVTC_GV2 0x018 /**< Generator Vertical Register 2 */ 00098 #define XVTC_GV3 0x01C /**< Generator Vertical Register 3 */ 00099 #define XVTC_GV4 0x020 /**< Generator Vertical Register 4 */ 00100 #define XVTC_GV5 0x024 /**< Generator Vertical Register 5 */ 00101 00102 #define XVTC_DS 0x028 /**< Detector Status Register */ 00103 00104 #define XVTC_DH0 0x02C /**< Detector Horizontal Register 0 */ 00105 #define XVTC_DH1 0x030 /**< Detector Horizontal Register 1 */ 00106 #define XVTC_DH2 0x034 /**< Detector Horizontal Register 2 */ 00107 #define XVTC_DV0 0x038 /**< Detector Vertical Register 0 */ 00108 #define XVTC_DV1 0x03C /**< Detector Vertical Register 1 */ 00109 #define XVTC_DV2 0x040 /**< Detector Vertical Register 2 */ 00110 #define XVTC_DV3 0x044 /**< Detector Vertical Register 3 */ 00111 #define XVTC_DV4 0x048 /**< Detector Vertical Register 4 */ 00112 #define XVTC_DV5 0x04C /**< Detector Vertical Register 5 */ 00113 00114 #define XVTC_FS00 0x050 /**< Frame Sync 00 Config Register */ 00115 #define XVTC_FS01 0x054 /**< Frame Sync 01 Config Register */ 00116 #define XVTC_FS02 0x058 /**< Frame Sync 02 Config Register */ 00117 #define XVTC_FS03 0x05C /**< Frame Sync 03 Config Register */ 00118 #define XVTC_FS04 0x060 /**< Frame Sync 04 Config Register */ 00119 #define XVTC_FS05 0x064 /**< Frame Sync 05 Config Register */ 00120 #define XVTC_FS06 0x068 /**< Frame Sync 06 Config Register */ 00121 #define XVTC_FS07 0x06C /**< Frame Sync 07 Config Register */ 00122 #define XVTC_FS08 0x070 /**< Frame Sync 08 Config Register */ 00123 #define XVTC_FS09 0x074 /**< Frame Sync 09 Config Register */ 00124 #define XVTC_FS10 0x078 /**< Frame Sync 10 Config Register */ 00125 #define XVTC_FS11 0x07C /**< Frame Sync 11 Config Register */ 00126 #define XVTC_FS12 0x080 /**< Frame Sync 12 Config Register */ 00127 #define XVTC_FS13 0x084 /**< Frame Sync 13 Config Register */ 00128 #define XVTC_FS14 0x088 /**< Frame Sync 14 Config Register */ 00129 #define XVTC_FS15 0x08C /**< Frame Sync 15 Config Register */ 00130 00131 #define XVTC_GGD 0x090 /**< Generator Global Delay register */ 00132 00133 #define XVTC_GVBHO0 0x0A0 /**< Generator VBlank Hori Offset 0 register */ 00134 #define XVTC_GVSHO0 0x0A4 /**< Generator VSync Hori Offset 0 register */ 00135 #define XVTC_GVBHO1 0x0A8 /**< Generator VBlank Hori Offset 1 register */ 00136 #define XVTC_GVSHO1 0x0AC /**< Generator VSync Hori Offset 1 register */ 00137 00138 #define XVTC_DVBHO0 0x0B0 /**< Detector VBlank Hori Offset 0 register */ 00139 #define XVTC_DVSHO0 0x0B4 /**< Detector VSync Hori Offset 0 register */ 00140 #define XVTC_DVBHO1 0x0B8 /**< Detector VBlank Hori Offset 1 register */ 00141 #define XVTC_DVSHO1 0x0BC /**< Detector VSync Hori Offset 1 register */ 00142 00143 #define XVTC_VER 0x0F0 /**< Version Register */ 00144 #define XVTC_RESET 0x100 /**< Reset Register */ 00145 #define XVTC_GIER 0x21C /**< Global Interrupt Enable Register */ 00146 #define XVTC_ISR 0x220 /**< Interrupt Status Register */ 00147 #define XVTC_IER 0x228 /**< Interrupt Enable Register */ 00148 /*@}*/ 00149 00150 /** @name Control Register bit definition 00151 * @{ 00152 */ 00153 #define XVTC_CTL_ACP_MASK 0x04000000 /**< Active Chroma Output Polarity*/ 00154 #define XVTC_CTL_AVP_MASK 0x02000000 /**< Active Video Output Polarity */ 00155 #define XVTC_CTL_FIP_MASK 0x01000000 /**< Field ID Output Polarity */ 00156 #define XVTC_CTL_VBP_MASK 0x00800000 /**< Vertical Blank Output Polarity 00157 */ 00158 #define XVTC_CTL_VSP_MASK 0x00400000 /**< Vertical Sync Output Polarity 00159 */ 00160 #define XVTC_CTL_HBP_MASK 0x00200000 /**< Horizontal Blank Output 00161 * Polarity */ 00162 #define XVTC_CTL_HSP_MASK 0x00100000 /**< Horizontal Sync Output Polarity 00163 */ 00164 #define XVTC_CTL_ALLP_MASK 0x07F00000 /**< Bit mask for all polarity bits 00165 */ 00166 #define XVTC_CTL_VCSS_MASK 0x00040000 /**< Start of Active Chroma Register 00167 * Source Select */ 00168 #define XVTC_CTL_VASS_MASK 0x00020000 /**< Vertical Active Video Start 00169 * Register Source Select */ 00170 #define XVTC_CTL_VBSS_MASK 0x00010000 /**< Vertical Back Porch Start 00171 * Register Source Select */ 00172 #define XVTC_CTL_VSSS_MASK 0x00008000 /**< Vertical Sync Start Register 00173 * Source Select */ 00174 #define XVTC_CTL_VFSS_MASK 0x00004000 /**< Vertical Front Porch Start 00175 * Register Source Select */ 00176 #define XVTC_CTL_VTSS_MASK 0x00002000 /**< Vertical Total Register Source 00177 * Select */ 00178 #define XVTC_CTL_HASS_MASK 0x00001000 /**< Horizontal Active Video Start 00179 * Register Source Select */ 00180 #define XVTC_CTL_HBSS_MASK 0x00000800 /**< Horizontal Back Porch Start 00181 * Register Source Select */ 00182 #define XVTC_CTL_HSSS_MASK 0x00000400 /**< Horizontal Sync Start Register 00183 * Source Select */ 00184 #define XVTC_CTL_HFSS_MASK 0x00000200 /**< Horizontal Front Porch Start 00185 * Register Source Select */ 00186 #define XVTC_CTL_HTSS_MASK 0x00000100 /**< Horizontal Total Register 00187 * Source Select */ 00188 #define XVTC_CTL_ALLSS_MASK 0x0007FF00 /**< Bit mask for all source select 00189 */ 00190 #define XVTC_CTL_GACPS_MASK 0x00000020 /**< Generator Active Chroma Pixel 00191 * Skip */ 00192 #define XVTC_CTL_GACLS_MASK 0x00000010 /**< Generator Active Chroma Line 00193 * Skip */ 00194 #define XVTC_CTL_LP_MASK 0x00000008 /**< Lock Polarity */ 00195 #define XVTC_CTL_SE_MASK 0x00000004 /**< Enable Sync with Detector */ 00196 #define XVTC_CTL_DE_MASK 0x00000002 /**< VTC Detector Enable */ 00197 #define XVTC_CTL_GE_MASK 0x00000001 /**< VTC Generator Enable */ 00198 /*@}*/ 00199 00200 /** @name VTC Generator Horizontal 0 00201 * @{ 00202 */ 00203 #define XVTC_GH0_FPSTART_MASK 0x1FFF0000 /**< Horizontal Front Porch Start 00204 * Cycle Count */ 00205 #define XVTC_GH0_FPSTART_SHIFT 16 /**< Bit shift for Horizontal 00206 * Front Porch Start Cycle 00207 * Count */ 00208 #define XVTC_GH0_TOTAL_MASK 0x00001FFF /**< Total clock cycles per Line 00209 */ 00210 /*@}*/ 00211 00212 /** @name VTC Generator Horizontal 1 00213 * @{ 00214 */ 00215 #define XVTC_GH1_BPSTART_MASK 0x1FFF0000 /**< Horizontal Back Porch Start 00216 * Cycle Count */ 00217 #define XVTC_GH1_BPSTART_SHIFT 16 /**< Bit shift for Horizontal Back 00218 * Porch Start Cycle Count */ 00219 #define XVTC_GH1_SYNCSTART_MASK 0x00001FFF /**< Horizontal Sync Start Cycle 00220 * Count */ 00221 /*@}*/ 00222 00223 /** @name VTC Generator Horizontal 2 00224 * @{ 00225 */ 00226 #define XVTC_GH2_ACTIVESTART_MASK 0x00001FFF /**< Horizontal Active Video Start 00227 * Cycle Count */ 00228 /*@}*/ 00229 00230 /** @name VTC Generator Vertical 0 (Field 0) 00231 * @{ 00232 */ 00233 #define XVTC_GV0_FPSTART_MASK 0x1FFF0000 /**< Vertical Front Porch Start 00234 * Cycle Count */ 00235 #define XVTC_GV0_FPSTART_SHIFT 16 /**< Bit shift for Vertical Front 00236 * Porch Start Cycle Count */ 00237 #define XVTC_GV0_TOTAL_MASK 0x00001FFF /**< Total lines per Frame */ 00238 /*@}*/ 00239 00240 /** @name VTC Generator Vertical 1 (Field 0) 00241 * @{ 00242 */ 00243 #define XVTC_GV1_BPSTART_MASK 0x1FFF0000 /**< Vertical Back Porch Start 00244 * Cycle Count */ 00245 #define XVTC_GV1_BPSTART_SHIFT 16 /**< Bit shift for Vertical Back 00246 * Porch Start Cycle Count */ 00247 #define XVTC_GV1_SYNCSTART_MASK 0x00001FFF /**< Vertical Sync Start Cycle 00248 * Count */ 00249 /*@}*/ 00250 00251 /** @name VTC Generator Vertical 2 (Field 0) 00252 * @{ 00253 */ 00254 #define XVTC_GV2_CHROMASTART_MASK 0x1FFF0000 /**< Active Chroma Start Line 00255 * Count */ 00256 #define XVTC_GV2_CHROMASTART_SHIFT 16 /**< Bit shift for Active Chroma 00257 * Start Line Count */ 00258 #define XVTC_GV2_ACTIVESTART_MASK 0x00001FFF /**< Vertical Active Video Start 00259 * Cycle Count */ 00260 /*@}*/ 00261 00262 /** @name VTC Generator Vertical 3 (Field 1) 00263 * @{ 00264 */ 00265 #define XVTC_GV3_FPSTART_MASK 0x1FFF0000 /**< Vertical Front Porch Start 00266 * Cycle Count */ 00267 #define XVTC_GV3_FPSTART_SHIFT 16 /**< Bit shift for Vertical Front 00268 * Porch Start Cycle Count */ 00269 #define XVTC_GV3_TOTAL_MASK 0x00001FFF /**< Total lines per Frame */ 00270 /*@}*/ 00271 00272 /** @name VTC Generator Vertical 4 (Field 1) 00273 * @{ 00274 */ 00275 #define XVTC_GV4_BPSTART_MASK 0x1FFF0000 /**< Vertical Back Porch Start 00276 * Cycle Count */ 00277 #define XVTC_GV4_BPSTART_SHIFT 16 /**< Bit shift for Vertical Back 00278 * Porch Start Cycle Count */ 00279 #define XVTC_GV4_SYNCSTART_MASK 0x00001FFF /**< Vertical Sync Start Cycle 00280 * Count */ 00281 /*@}*/ 00282 00283 /** @name VTC Generator Vertical 5 (Field 1) 00284 * @{ 00285 */ 00286 #define XVTC_GV5_CHROMASTART_MASK 0x1FFF0000 /**< Active Chroma Start Line 00287 * Count */ 00288 #define XVTC_GV5_CHROMASTART_SHIFT 16 /**< Bit shift for Active Chroma 00289 * Start Line Count */ 00290 #define XVTC_GV5_ACTIVESTART_MASK 0x00001FFF /**< Vertical Active Video Start 00291 * Cycle Count */ 00292 /*@}*/ 00293 00294 /** @name VTC Detector Status 00295 * @{ 00296 */ 00297 #define XVTC_DS_AC_POL_MASK 0x04000000 /**< Active Chroma Output Polarity 00298 */ 00299 #define XVTC_DS_AV_POL_MASK 0x02000000 /**< Active Video Output Polarity 00300 */ 00301 #define XVTC_DS_FID_POL_MASK 0x01000000 /**< Field ID Output Polarity */ 00302 #define XVTC_DS_VBLANK_POL_MASK 0x00800000 /**< Vertical Blank Output 00303 * Polarity */ 00304 #define XVTC_DS_VSYNC_POL_MASK 0x00400000 /**< Vertical Sync Output Polarity 00305 */ 00306 #define XVTC_DS_HBLANK_POL_MASK 0x00200000 /**< Horizontal Blank Output 00307 * Polarity */ 00308 #define XVTC_DS_HSYNC_POL_MASK 0x00100000 /**< Horizontal Sync Output 00309 * Polarity */ 00310 #define XVTC_DS_ACSKIP_MASK 0x00000010 /**< Detector Active Chroma Skip 00311 */ 00312 /*@}*/ 00313 00314 /** @name VTC Detector Horizontal 0 00315 * @{ 00316 */ 00317 #define XVTC_DH0_FPSTART_MASK 0x1FFF0000 /**< Detected Horizontal Front 00318 * Porch Start Cycle Count */ 00319 #define XVTC_DH0_FPSTART_SHIFT 16 /**< Bit shift for Detected 00320 * Horizontal Front Porch Start 00321 * Cycle Count */ 00322 #define XVTC_DH0_TOTAL_MASK 0x00001FFF /**< Detected Total clock cycles 00323 * per Line */ 00324 /*@}*/ 00325 00326 /** @name VTC Detector Horizontal 1 00327 * @{ 00328 */ 00329 #define XVTC_DH1_BPSTART_MASK 0x1FFF0000 /**< Detected Horizontal Back 00330 * Porch Start Cycle Count */ 00331 #define XVTC_DH1_BPSTART_SHIFT 16 /**< Bit shift for Detected 00332 * Horizontal Back Porch Start 00333 * Cycle Count */ 00334 #define XVTC_DH1_SYNCSTART_MASK 0x00001FFF /**< Detected Horizontal Sync 00335 * Start Cycle Count */ 00336 /*@}*/ 00337 00338 /** @name VTC Detector Horizontal 2 00339 * @{ 00340 */ 00341 #define XVTC_DH2_ACTIVESTART_MASK 0x00001FFF /**< Detected Horizontal Active 00342 * Video Start Cycle Count */ 00343 /*@}*/ 00344 00345 /** @name VTC Detector Vertical 0 (Field 0) 00346 * @{ 00347 */ 00348 #define XVTC_DV0_FPSTART_MASK 0x1FFF0000 /**< Detected Vertical Front Porch 00349 * Start Cycle Count */ 00350 #define XVTC_DV0_FPSTART_SHIFT 16 /**< Bit shift for Detected 00351 * Vertical Front Porch Start 00352 * Cycle Count */ 00353 #define XVTC_DV0_TOTAL_MASK 0x00001FFF /**< Detected Total lines per 00354 * Frame */ 00355 /*@}*/ 00356 00357 /** @name VTC Detector Vertical 1 (Field 0) 00358 * @{ 00359 */ 00360 #define XVTC_DV1_BPSTART_MASK 0x1FFF0000 /**< Detected Vertical Back Porch 00361 * Start Cycle Count */ 00362 #define XVTC_DV1_BPSTART_SHIFT 16 /**< Bit shift for Detected 00363 * Vertical Back Porch Start 00364 * Cycle Count */ 00365 #define XVTC_DV1_SYNCSTART_MASK 0x00001FFF /**< Detected Vertical Sync Start 00366 * Cycle Count */ 00367 /*@}*/ 00368 00369 /** @name VTC Detector Vertical 2 (Field 0) 00370 * @{ 00371 */ 00372 #define XVTC_DV2_CHROMASTART_MASK 0x1FFF0000 /**< Detected Active Chroma Start 00373 * Line Count */ 00374 #define XVTC_DV2_CHROMASTART_SHIFT 16 /**< Bit shift for Detected Active 00375 * Chroma Start Line Count */ 00376 #define XVTC_DV2_ACTIVESTART_MASK 0x00001FFF /**< Detected Vertical Active 00377 * Video Start Cycle Count */ 00378 /*@}*/ 00379 00380 /** @name VTC Detector Vertical 3 (Field 1) 00381 * @{ 00382 */ 00383 #define XVTC_DV3_FPSTART_MASK 0x1FFF0000 /**< Detected Vertical Front Porch 00384 * Start Cycle Count */ 00385 #define XVTC_DV3_FPSTART_SHIFT 16 /**< Bit shift for Detected 00386 * Vertical Front Porch Start 00387 * Cycle Count */ 00388 #define XVTC_DV3_TOTAL_MASK 0x00001FFF /**< Detected Total lines per 00389 * Frame */ 00390 /*@}*/ 00391 00392 /** @name VTC Detector Vertical 4 (Field 1) 00393 * @{ 00394 */ 00395 #define XVTC_DV4_BPSTART_MASK 0x1FFF0000 /**< Detected Vertical Back Porch 00396 * Start Cycle Count */ 00397 #define XVTC_DV4_BPSTART_SHIFT 16 /**< Bit shift for Detected 00398 * Vertical Back Porch Start 00399 * Cycle Count */ 00400 #define XVTC_DV4_SYNCSTART_MASK 0x00001FFF /**< Detected Vertical Sync Start 00401 * Cycle Count */ 00402 /*@}*/ 00403 00404 /** @name VTC Detector Vertical 5 (Field 1) 00405 * @{ 00406 */ 00407 #define XVTC_DV5_CHROMASTART_MASK 0x1FFF0000 /**< Detected Active Chroma Start 00408 * Line Count */ 00409 #define XVTC_DV5_CHROMASTART_SHIFT 16 /**< Bit shift for Detected Active 00410 * Chroma Start Line Count */ 00411 #define XVTC_DV5_ACTIVESTART_MASK 0x00001FFF /**< Detected Vertical Active 00412 * Video Start Cycle Count */ 00413 /*@}*/ 00414 00415 /** @name VTC Frame Sync 00 --- 15 00416 * @{ 00417 */ 00418 #define XVTC_FSXX_VSTART_MASK 0x1FFF0000 /**< Vertical line count during 00419 * which current Frame Sync is 00420 * active */ 00421 #define XVTC_FSXX_VSTART_SHIFT 16 /**< Bit shift for the vertical 00422 * line count */ 00423 #define XVTC_FSXX_HSTART_MASK 0x00001FFF /**< Horizontal cycle count during 00424 * which current Frame Sync is 00425 * active */ 00426 /*@}*/ 00427 00428 /** @name VTC Generator Global Delay 00429 * @{ 00430 */ 00431 #define XVTC_GGD_VDELAY_MASK 0x1FFF0000 /**< Total lines per frame to delay 00432 * generator output */ 00433 #define XVTC_GGD_VDELAY_SHIFT 16 /**< Bit shift for the total 00434 * lines */ 00435 #define XVTC_GGD_HDELAY_MASK 0x00001FFF /**< Total clock cycles per line to 00436 * delay generator output */ 00437 /*@}*/ 00438 00439 /** @name VTC Generator/Detector VBlank/VSync Hori. Offset registers 00440 * @{ 00441 */ 00442 #define XVTC_XVXHOX_HEND_MASK 0x1FFF0000 /**< Horizontal Offset End */ 00443 #define XVTC_XVXHOX_HEND_SHIFT 16 /**< Horizontal Offset End Shift */ 00444 #define XVTC_XVXHOX_HSTART_MASK 0x00001FFF /**< Horizontal Offset Start */ 00445 /*@}*/ 00446 00447 /** @name Reset Register bit definition 00448 * @{ 00449 */ 00450 #define XVTC_RESET_RESET_MASK 0x0000000A /**< Software Reset */ 00451 /*@}*/ 00452 00453 /** @name Version Register bit definition 00454 * @{ 00455 */ 00456 #define XVTC_VER_MAJOR_MASK 0xF0000000 /**< Major Version*/ 00457 #define XVTC_VER_MAJOR_SHIFT 28 /**< Major Version Bit Shift*/ 00458 #define XVTC_VER_MINOR_MASK 0x0FF00000 /**< Minor Version */ 00459 #define XVTC_VER_MINOR_SHIFT 20 /**< Minor Version Bit Shift*/ 00460 #define XVTC_VER_REV_MASK 0x000F0000 /**< Revision Version */ 00461 #define XVTC_VER_REV_SHIFT 16 /**< Revision Bit Shift*/ 00462 /*@}*/ 00463 00464 /** @name Global Interrupt Enable Register bit definition 00465 * @{ 00466 */ 00467 #define XVTC_GIER_GIE_MASK 0x80000000 /**< Global interrupt enable */ 00468 /*@}*/ 00469 00470 /** @name Interrupt Status/Enable Register bit definition 00471 * @{ 00472 */ 00473 #define XVTC_IXR_FSYNC15_MASK 0x80000000 /**< Frame Sync Interrupt 15 */ 00474 #define XVTC_IXR_FSYNC14_MASK 0x40000000 /**< Frame Sync Interrupt 14 */ 00475 #define XVTC_IXR_FSYNC13_MASK 0x20000000 /**< Frame Sync Interrupt 13 */ 00476 #define XVTC_IXR_FSYNC12_MASK 0x10000000 /**< Frame Sync Interrupt 12 */ 00477 #define XVTC_IXR_FSYNC11_MASK 0x08000000 /**< Frame Sync Interrupt 11 */ 00478 #define XVTC_IXR_FSYNC10_MASK 0x04000000 /**< Frame Sync Interrupt 10 */ 00479 #define XVTC_IXR_FSYNC09_MASK 0x02000000 /**< Frame Sync Interrupt 09 */ 00480 #define XVTC_IXR_FSYNC08_MASK 0x01000000 /**< Frame Sync Interrupt 08 */ 00481 #define XVTC_IXR_FSYNC07_MASK 0x00800000 /**< Frame Sync Interrupt 07 */ 00482 #define XVTC_IXR_FSYNC06_MASK 0x00400000 /**< Frame Sync Interrupt 06 */ 00483 #define XVTC_IXR_FSYNC05_MASK 0x00200000 /**< Frame Sync Interrupt 05 */ 00484 #define XVTC_IXR_FSYNC04_MASK 0x00100000 /**< Frame Sync Interrupt 04 */ 00485 #define XVTC_IXR_FSYNC03_MASK 0x00080000 /**< Frame Sync Interrupt 03 */ 00486 #define XVTC_IXR_FSYNC02_MASK 0x00040000 /**< Frame Sync Interrupt 02 */ 00487 #define XVTC_IXR_FSYNC01_MASK 0x00020000 /**< Frame Sync Interrupt 01 */ 00488 #define XVTC_IXR_FSYNC00_MASK 0x00010000 /**< Frame Sync Interrupt 00 */ 00489 #define XVTC_IXR_FSYNCALL_MASK 0xFFFF0000 /**< All Frame Sync Interrupt 0-15*/ 00490 00491 #define XVTC_IXR_G_AV_MASK 0x00002000 /**< Generator Active Video Intr */ 00492 #define XVTC_IXR_G_VBLANK_MASK 0x00001000 /**< Generator VBLANK Interrupt */ 00493 #define XVTC_IXR_G_ALL_MASK 0x00003000 /**< All Generator interrupts */ 00494 00495 #define XVTC_IXR_D_AV_MASK 0x00000200 /**< Detector Active Video Intr */ 00496 #define XVTC_IXR_D_VBLANK_MASK 0x00000100 /**< Detector VBLANK Interrupt */ 00497 #define XVTC_IXR_D_ALL_MASK 0x00000300 /**< All Detector interrupts */ 00498 00499 #define XVTC_IXR_AL_MASK 0x00000080 /**< All lock */ 00500 #define XVTC_IXR_ACL_MASK 0x00000040 /**< Active Chroma signal lock */ 00501 #define XVTC_IXR_AVL_MASK 0x00000020 /**< Active Video Signal Lock */ 00502 #define XVTC_IXR_FIL_MASK 0x00000010 /**< Field ID Signal Lock */ 00503 #define XVTC_IXR_VBL_MASK 0x00000008 /**< Vertical Blank Signal Lock */ 00504 #define XVTC_IXR_VSL_MASK 0x00000004 /**< Vertical Sync Signal Lock */ 00505 #define XVTC_IXR_HBL_MASK 0x00000002 /**< Horizontal Blank Signal Lock */ 00506 #define XVTC_IXR_HSL_MASK 0x00000001 /**< Horizontal Sync Signal Lock */ 00507 #define XVTC_IXR_LOCKALL_MASK 0x000000FF /**< All Signal Lock interrupt */ 00508 #define XVTC_IXR_ALLINTR_MASK (XVTC_IXR_FSYNCALL_MASK | \ 00509 XVTC_IXR_G_ALL_MASK | \ 00510 XVTC_IXR_D_ALL_MASK | \ 00511 XVTC_IXR_LOCKALL_MASK) /**< Mask for 00512 * all 00513 * interrupts 00514 */ 00515 /*@}*/ 00516 00517 /**************************** Type Definitions *******************************/ 00518 00519 00520 /***************** Macros (Inline Functions) Definitions *********************/ 00521 00522 /** @name Register Access Macro Definition 00523 * @{ 00524 */ 00525 #define XVtc_In32 XIo_In32 00526 #define XVtc_Out32 XIo_Out32 00527 00528 /*****************************************************************************/ 00529 /** 00530 * 00531 * Read the given register. 00532 * 00533 * @param BaseAddress is the base address of the device 00534 * @param RegOffset is the register offset to be read 00535 * 00536 * @return The 32-bit value of the register 00537 * 00538 * @note 00539 * C-style signature: 00540 * u32 XVtc_ReadReg(u32 BaseAddress, u32 RegOffset) 00541 * 00542 ******************************************************************************/ 00543 #define XVtc_ReadReg(BaseAddress, RegOffset) \ 00544 XVtc_In32((BaseAddress) + (RegOffset)) 00545 00546 /*****************************************************************************/ 00547 /** 00548 * 00549 * Write the given register. 00550 * 00551 * @param BaseAddress is the base address of the device 00552 * @param RegOffset is the register offset to be written 00553 * @param Data is the 32-bit value to write to the register 00554 * 00555 * @return None. 00556 * 00557 * @note 00558 * C-style signature: 00559 * void XVtc_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) 00560 * 00561 ******************************************************************************/ 00562 #define XVtc_WriteReg(BaseAddress, RegOffset, Data) \ 00563 XVtc_Out32((BaseAddress) + (RegOffset), (Data)) 00564 00565 /*@}*/ 00566 00567 /************************** Function Prototypes ******************************/ 00568 00569 #ifdef __cplusplus 00570 } 00571 #endif 00572 00573 #endif /* end of protection macro */