Xilinx TimeBase Device Driver Documentation
ver 1.01.a
Introduction
This is the Xilinx MVI TimeBase device driver.
The TimeBase device detects timebase signals, independently overrides any one of them, re-generates timebase signals with +/- delay and with polarity inversion, and generates up to 16 one cycle Frame Sync outputs.
The device has the following main features:
- Detect timebase signals:
- horizontal sync
- horizontal blank
- vertical sync
- vertical blank
- active video
- field id
- Independently override any one signal.
- Re-generate timebase signals with +/- delay and with polarity inversion.
- Generate up to 16 one cycle Frame Sync outputs.
For a full description of TimeBase features, please see the hardware specification.
Interrupt Service
The interrupt types supported are:
- Frame Sync Interrupts 0 - 15
- Generator interrupt
- Generator Active Video Interrupt
- Generator VBLANK Interrupt
- Detector interrupt:
- Detector Active Video Interrupt
- Detector VBLANK Interrupt
- Signal Lock interrupt
- Active Chroma signal lock
- Active Video Signal Lock
- Field ID Signal Lock
- Vertical Blank Signal Lock
- Vertical Sync Signal Lock
- Horizontal Blank Signal Lock
- Horizontal Sync Signal Lock
Software Initialization
The application needs to do following steps in order for preparing the TimeBase to be ready to process timebase signal handling.
Examples
An example is provided with this driver to demonstrate the driver usage.
Cache Coherency
Alignment
Limitations
BUS Interface
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