00001 /* $Id: */ 00002 /****************************************************************************** 00003 * 00004 * (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. 00005 * 00006 * This file contains confidential and proprietary information 00007 * of Xilinx, Inc. and is protected under U.S. and 00008 * international copyright and other intellectual property 00009 * laws. 00010 * 00011 * DISCLAIMER 00012 * This disclaimer is not a license and does not grant any 00013 * rights to the materials distributed herewith. Except as 00014 * otherwise provided in a valid license issued to you by 00015 * Xilinx, and to the maximum extent permitted by applicable 00016 * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 00017 * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 00018 * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 00019 * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 00020 * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 00021 * (2) Xilinx shall not be liable (whether in contract or tort, 00022 * including negligence, or under any other theory of 00023 * liability) for any loss or damage of any kind or nature 00024 * related to, arising under or in connection with these 00025 * materials, including for any direct, or any indirect, 00026 * special, incidental, or consequential loss or damage 00027 * (including loss of data, profits, goodwill, or any type of 00028 * loss or damage suffered as a result of any action brought 00029 * by a third party) even if such damage or loss was 00030 * reasonably foreseeable or Xilinx had been advised of the 00031 * possibility of the same. 00032 * 00033 * CRITICAL APPLICATIONS 00034 * Xilinx products are not designed or intended to be fail- 00035 * safe, or for use in any application requiring fail-safe 00036 * performance, such as life-support or safety devices or 00037 * systems, Class III medical devices, nuclear facilities, 00038 * applications related to the deployment of airbags, or any 00039 * other applications that could lead to death, personal 00040 * injury, or severe property or environmental damage 00041 * (individually and collectively, "Critical 00042 * Applications"). Customer assumes the sole risk and 00043 * liability of any use of Xilinx products in Critical 00044 * Applications, subject only to applicable laws and 00045 * regulations governing limitations on product liability. 00046 * 00047 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 00048 * PART OF THIS FILE AT ALL TIMES. 00049 * 00050 ******************************************************************************/ 00051 /*****************************************************************************/ 00052 /** 00053 * 00054 * @file xosd_hw.h 00055 * 00056 * This header file contains identifiers and register-level driver functions (or 00057 * macros) that can be used to access the Xilinx MVI Video On-Screen-Display 00058 * (OSD) device. 00059 * 00060 * For more information about the operation of this device, see the hardware 00061 * specification and documentation in the higher level driver xosd.h source 00062 * code file. 00063 * 00064 * <pre> 00065 * MODIFICATION HISTORY: 00066 * 00067 * Ver Who Date Changes 00068 * ----- ---- -------- ------------------------------------------------------- 00069 * 1.00a xd 08/01/08 First release 00070 * </pre> 00071 * 00072 ******************************************************************************/ 00073 00074 #ifndef XOSD_HW_H /* prevent circular inclusions */ 00075 #define XOSD_HW_H /* by using protection macros */ 00076 00077 #ifdef __cplusplus 00078 extern "C" { 00079 #endif 00080 00081 /***************************** Include Files *********************************/ 00082 00083 #include "xio.h" 00084 00085 /************************** Constant Definitions *****************************/ 00086 00087 /** @name Register Offsets 00088 * @{ 00089 */ 00090 #define XOSD_CTL 0x000 /**< Control */ 00091 #define XOSD_SS 0x010 /**< Screen Size */ 00092 #define XOSD_BC0 0x014 /**< Background Color Channel 0 */ 00093 #define XOSD_BC1 0x018 /**< Background Color Channel 1 */ 00094 #define XOSD_BC2 0x01C /**< Background Color Channel 2 */ 00095 00096 #define XOSD_L0C 0x020 /**< Layer 0 Control */ 00097 #define XOSD_L0P 0x024 /**< Layer 0 Position */ 00098 #define XOSD_L0S 0x028 /**< Layer 0 Size */ 00099 00100 #define XOSD_L1C 0x030 /**< Layer 1 Control */ 00101 #define XOSD_L1P 0x034 /**< Layer 1 Position */ 00102 #define XOSD_L1S 0x038 /**< Layer 1 Size */ 00103 00104 #define XOSD_L2C 0x040 /**< Layer 2 Control */ 00105 #define XOSD_L2P 0x044 /**< Layer 2 Position */ 00106 #define XOSD_L2S 0x048 /**< Layer 2 Size */ 00107 00108 #define XOSD_L3C 0x050 /**< Layer 3 Control */ 00109 #define XOSD_L3P 0x054 /**< Layer 3 Position */ 00110 #define XOSD_L3S 0x058 /**< Layer 3 Size */ 00111 00112 #define XOSD_L4C 0x060 /**< Layer 4 Control */ 00113 #define XOSD_L4P 0x064 /**< Layer 4 Position */ 00114 #define XOSD_L4S 0x068 /**< Layer 4 Size */ 00115 00116 #define XOSD_L5C 0x070 /**< Layer 5 Control */ 00117 #define XOSD_L5P 0x074 /**< Layer 5 Position */ 00118 #define XOSD_L5S 0x078 /**< Layer 5 Size */ 00119 00120 #define XOSD_L6C 0x080 /**< Layer 6 Control */ 00121 #define XOSD_L6P 0x084 /**< Layer 6 Position */ 00122 #define XOSD_L6S 0x088 /**< Layer 6 Size */ 00123 00124 #define XOSD_L7C 0x090 /**< Layer 7 Control */ 00125 #define XOSD_L7P 0x094 /**< Layer 7 Position */ 00126 #define XOSD_L7S 0x098 /**< Layer 7 Size */ 00127 00128 #define XOSD_GCWBA 0x0A0 /**< GPU Write Bank Address */ 00129 #define XOSD_GCABA 0x0A4 /**< GPU Active Bank Address */ 00130 #define XOSD_GCD 0x0A8 /**< GPU Data */ 00131 00132 #define XOSD_VER 0x0F0 /**< Version Register */ 00133 #define XOSD_RST 0x100 /**< Software Reset */ 00134 00135 #define XOSD_GIER 0x21C /**< Global Interrupt Enable Register */ 00136 #define XOSD_ISR 0x220 /**< Interrupt Status Register */ 00137 #define XOSD_IER 0x228 /**< Interrupt Enable Register */ 00138 /*@}*/ 00139 00140 /** @name Memory footprint of layers 00141 * @{ 00142 */ 00143 #define XOSD_LAYER_SIZE 0x10 00144 #define XOSD_LXC 0x00 /**< Layer Control */ 00145 #define XOSD_LXP 0x04 /**< Layer Position */ 00146 #define XOSD_LXS 0x08 /**< Layer Size */ 00147 /*@}*/ 00148 00149 /** @name Graphics Controller Bank related constants 00150 * @{ 00151 */ 00152 #define XOSD_GC_BANK_NUM 2 /**< The number of Banks in each 00153 * Graphics controller */ 00154 /*@}*/ 00155 00156 /** @name OSD Control Register bit definition 00157 * @{ 00158 */ 00159 #define XOSD_CTL_VBP_MASK 0x00000020 /**< Vertical Blank Polarity */ 00160 #define XOSD_CTL_HBP_MASK 0x00000010 /**< Horizontal Blank Polarity */ 00161 #define XOSD_CTL_RUE_MASK 0x00000004 /**< OSD Register Update Enable */ 00162 #define XOSD_CTL_EN_MASK 0x00000001 /**< OSD Enable */ 00163 /*@}*/ 00164 00165 /** @name OSD Screen Size Register bit definition 00166 * @{ 00167 */ 00168 #define XOSD_SS_YSIZE_MASK 0x0FFF0000 /**< Vertical Height of OSD Output */ 00169 #define XOSD_SS_YSIZE_SHIFT 16 /**< Bit shift of XOSD_SS_YSIZE_MASK */ 00170 #define XOSD_SS_XSIZE_MASK 0x00000FFF /**< Horizontal Width of OSD Output */ 00171 /*@}*/ 00172 00173 /** @name OSD Background Color Channel 0 00174 * @{ 00175 */ 00176 #define XOSD_BC0_YG_MASK 0x000003FF /**< Y (luma) or Green */ 00177 /*@}*/ 00178 00179 /** @name OSD Background Color Channel 1 00180 * @{ 00181 */ 00182 #define XOSD_BC1_UCBB_MASK 0x000003FF /**< U (Cb) or Blue */ 00183 /*@}*/ 00184 00185 /** @name OSD Background Color Channel 2 00186 * @{ 00187 */ 00188 #define XOSD_BC2_VCRR_MASK 0x000003FF /**< V(Cr) or Red */ 00189 /*@}*/ 00190 00191 /** @name Maximum number of the layers 00192 * @{ 00193 */ 00194 #define XOSD_MAX_NUM_OF_LAYERS 8 /**< The max number of layers */ 00195 /*@}*/ 00196 00197 /** @name OSD Layer Control (Layer 0 through (XOSD_MAX_NUM_OF_LAYERS - 1)) 00198 * @{ 00199 */ 00200 #define XOSD_LXC_ALPHA_MASK 0x00FF0000 /**< Global Alpha Value */ 00201 #define XOSD_LXC_ALPHA_SHIFT 16 /**< Bit shift number of Global 00202 * Alpha Value */ 00203 #define XOSD_LXC_PRIORITY_MASK 0x00000700 /**< Layer Priority */ 00204 #define XOSD_LXC_PRIORITY_SHIFT 8 /**< Bit shift number of Layer 00205 * Priority */ 00206 #define XOSD_LXC_GALPHAEN_MASK 0x00000002 /**< Global Alpha Enable */ 00207 #define XOSD_LXC_EN_MASK 0x00000001 /**< Layer Enable */ 00208 /*@}*/ 00209 00210 /** @name OSD Layer Position (Layer 0 through (XOSD_MAX_NUM_OF_LAYERS - 1)) 00211 * @{ 00212 */ 00213 #define XOSD_LXP_YSTART_MASK 0x0FFF0000 /**< Vertical start line of origin 00214 * of layer */ 00215 #define XOSD_LXP_YSTART_SHIFT 16 /**< Bit shift of vertical start 00216 * line of origin of layer */ 00217 #define XOSD_LXP_XSTART_MASK 0x00000FFF /**< Horizontal start pixel of 00218 * origin of layer */ 00219 /*@}*/ 00220 00221 /** @name OSD Layer Size (Layer 0 through (XOSD_MAX_NUM_OF_LAYERS - 1)) 00222 * @{ 00223 */ 00224 #define XOSD_LXS_YSIZE_MASK 0x0FFF0000 /**< Vertical size of layer */ 00225 #define XOSD_LXS_YSIZE_SHIFT 16 /**< Bit shift number of vertical 00226 * size of layer */ 00227 #define XOSD_LXS_XSIZE_MASK 0x00000FFF /**< Horizontal size of layer */ 00228 /*@}*/ 00229 00230 /** @name OSD Graphics Controller Write Bank Address 00231 * @{ 00232 */ 00233 #define XOSD_GCWBA_GCNUM_MASK 0x00000700 /**< Graphics Controller Number */ 00234 #define XOSD_GCWBA_GCNUM_SHIFT 8 /**< Bit shift of Graphics 00235 * Controller Number */ 00236 #define XOSD_GCWBA_BANK_MASK 0x00000007 /**< Controls which bank to write 00237 * GPU instructions and Color 00238 * LUT data into. */ 00239 00240 #define XOSD_GCWBA_INS0 0x00000000 /** Instruction RAM 0 */ 00241 #define XOSD_GCWBA_INS1 0x00000001 /** Instruction RAM 1 */ 00242 #define XOSD_GCWBA_COL0 0x00000002 /** Color LUT RAM 0 */ 00243 #define XOSD_GCWBA_COL1 0x00000003 /** Color LUT RAM 1 */ 00244 #define XOSD_GCWBA_TXT0 0x00000004 /** Text RAM 0 */ 00245 #define XOSD_GCWBA_TXT1 0x00000005 /** Text RAM 1 */ 00246 #define XOSD_GCWBA_CHR0 0x00000006 /** Character Set RAM 0 */ 00247 #define XOSD_GCWBA_CHR1 0x00000007 /** Character Set RAM 1 */ 00248 /*@}*/ 00249 00250 /** @name OSD Graphics Controller Active Bank Address 00251 * @{ 00252 */ 00253 #define XOSD_GCABA_CHR_MASK 0xFF000000 /**< Set the active Character Bank*/ 00254 #define XOSD_GCABA_CHR_SHIFT 24 /**< Bit shift of active Character 00255 * Bank */ 00256 #define XOSD_GCABA_TXT_MASK 0x00FF0000 /**< Set the active Text Bank */ 00257 #define XOSD_GCABA_TXT_SHIFT 16 /**< Bit shift of active Text Bank*/ 00258 #define XOSD_GCABA_COL_MASK 0x0000FF00 /**< Set the active Color Table 00259 * Bank */ 00260 #define XOSD_GCABA_COL_SHIFT 8 /**< Bit shift of active Color Table 00261 * Bank */ 00262 #define XOSD_GCABA_INS_MASK 0x000000FF /**< Set the active instruction Bank 00263 */ 00264 /*@}*/ 00265 00266 /** @name Version Register bit definition 00267 * @{ 00268 */ 00269 #define XOSD_VER_MAJOR_MASK 0xF0000000 /**< Major Version*/ 00270 #define XOSD_VER_MAJOR_SHIFT 28 /**< Major Version Bit Shift*/ 00271 #define XOSD_VER_MINOR_MASK 0x0FF00000 /**< Minor Version */ 00272 #define XOSD_VER_MINOR_SHIFT 20 /**< Minor Version Bit Shift*/ 00273 #define XOSD_VER_REV_MASK 0x000F0000 /**< Revision Version */ 00274 #define XOSD_VER_REV_SHIFT 16 /**< Revision Bit Shift*/ 00275 /*@}*/ 00276 00277 /** @name OSD Software Reset 00278 * @{ 00279 */ 00280 #define XOSD_RST_RESET 0x0000000A /**< Software Reset */ 00281 /*@}*/ 00282 00283 /** @name Global Interrupt Enable Register bit definition 00284 * @{ 00285 */ 00286 #define XOSD_GIER_GIE_MASK 0x80000000 /**< Global interrupt enable */ 00287 /*@}*/ 00288 00289 /** @name Interrupt Status/Enable Register bit definition 00290 * @{ 00291 */ 00292 #define XOSD_IXR_GAO_MASK 0xFF000000 /**< Graphics Controller Instruction 00293 * Overflow */ 00294 #define XOSD_IXR_GIE_MASK 0x00FF0000 /**< Graphics Controller Instruction 00295 * Error */ 00296 #define XOSD_IXR_OOE_MASK 0x00001000 /**< OSD Output Overflow Error */ 00297 #define XOSD_IXR_IUE_MASK 0x00000FF0 /**< OSD Input Underflow Error */ 00298 #define XOSD_IXR_VBIE_MASK 0x00000008 /**< Vertical Blank Interval End */ 00299 #define XOSD_IXR_VBIS_MASK 0x00000004 /**< Vertical Blank Interval Start*/ 00300 #define XOSD_IXR_FE_MASK 0x00000002 /**< OSD did not complete 00301 * processing frame before next 00302 * Vblank */ 00303 #define XOSD_IXR_FD_MASK 0x00000001 /**< OSD completed processing 00304 * Frame */ 00305 #define XOSD_IXR_ALLIERR_MASK (XOSD_IXR_GAO_MASK | \ 00306 XOSD_IXR_GIE_MASK | \ 00307 XOSD_IXR_OOE_MASK | \ 00308 XOSD_IXR_IUE_MASK | \ 00309 XOSD_IXR_FE_MASK) /**< Mask for all error 00310 * interrupts */ 00311 00312 #define XOSD_IXR_ALLINTR_MASK (XOSD_IXR_VBIE_MASK | \ 00313 XOSD_IXR_VBIS_MASK | \ 00314 XOSD_IXR_FD_MASK | \ 00315 XOSD_IXR_ALLIERR_MASK) /**< Mask for all 00316 * interrupts */ 00317 /*@}*/ 00318 00319 /** @name Layer Types 00320 * @{ 00321 */ 00322 #define XOSD_LAYER_TYPE_DISABLE 0 /**< Layer is disabled */ 00323 #define XOSD_LAYER_TYPE_GPU 1 /**< Layer's type is GPU */ 00324 #define XOSD_LAYER_TYPE_VFBC 2 /**< Layer's type is VFBC */ 00325 /*@}*/ 00326 00327 /** @name Supported Instruction numbers given an instruction memory size 00328 * @{ 00329 */ 00330 #define XOSD_INS_MEM_SIZE_TO_NUM 1 /**< Conversion to the number of 00331 * instructions from the 00332 * instruction memory size */ 00333 /*@}*/ 00334 00335 /** @name GC Instruction word offset definition 00336 * @{ 00337 */ 00338 #define XOSD_INS0 0 /**< Instruction word 0 offset */ 00339 #define XOSD_INS1 1 /**< Instruction word 1 offset */ 00340 #define XOSD_INS2 2 /**< Instruction word 2 offset */ 00341 #define XOSD_INS3 3 /**< Instruction word 3 offset */ 00342 #define XOSD_INS_SIZE 4 /**< Size of an instruction in words */ 00343 /*@}*/ 00344 00345 /** @name GC Instruction word 0 definition 00346 * @{ 00347 */ 00348 #define XOSD_INS0_OPCODE_MASK 0xF0000000 /**< Operation Code (OpCode) */ 00349 #define XOSD_INS0_OPCODE_SHIFT 28 /**< Bit shift number of OpCode */ 00350 #define XOSD_INS0_GCNUM_MASK 0x07000000 /**< Graphics controller number 00351 * (GC#) */ 00352 #define XOSD_INS0_GCNUM_SHIFT 24 /**< Bit shift number of GC# */ 00353 #define XOSD_INS0_XEND_MASK 0x00FFF000 /**< Horizontal end pixel of the 00354 * object */ 00355 #define XOSD_INS0_XEND_SHIFT 12 /**< Bit shift number of Horizontal 00356 * end pixel of the object */ 00357 #define XOSD_INS0_XSTART_MASK 0x00000FFF /**< Horizontal start pixel of the 00358 * Object */ 00359 /*@}*/ 00360 00361 /** @name GC Instruction word 1 definition 00362 * @{ 00363 */ 00364 #define XOSD_INS1_TXTINDEX_MASK 0x0000000F /**< String Index */ 00365 /*@}*/ 00366 00367 /** @name GC Instruction word 2 definition 00368 * @{ 00369 */ 00370 #define XOSD_INS2_OBJSIZE_MASK 0xFF000000 /**< Object Size */ 00371 #define XOSD_INS2_OBJSIZE_SHIFT 24 /**< Bit shift number of Object 00372 * Size */ 00373 #define XOSD_INS2_YEND_MASK 0x00FFF000 /**< Vertical end line of the 00374 * object */ 00375 #define XOSD_INS2_YEND_SHIFT 12 /**< Bit shift number of Vertical 00376 * end line of the object */ 00377 #define XOSD_INS2_YSTART_MASK 0x00000FFF /**< Vertical start line of the 00378 * Object */ 00379 /*@}*/ 00380 00381 /** @name GC Instruction word 3 definition 00382 * @{ 00383 */ 00384 #define XOSD_INS3_COL_MASK 0x0000000F /**< Color Index for Box/Text */ 00385 /*@}*/ 00386 00387 /** @name GC Instruction Operation Code definition (used in Instruction word 0) 00388 * @{ 00389 */ 00390 #define XOSD_INS_OPCODE_END 0x0 /**< End of instruction list */ 00391 #define XOSD_INS_OPCODE_NOP 0x8 /**< NOP */ 00392 #define XOSD_INS_OPCODE_BOX 0xA /**< Box */ 00393 #define XOSD_INS_OPCODE_LINE 0xC /**< Line */ 00394 #define XOSD_INS_OPCODE_TXT 0xE /**< Text */ 00395 #define XOSD_INS_OPCODE_BOXTXT 0xF /**< Box Text */ 00396 /*@}*/ 00397 00398 /** @name GC color size 00399 * @{ 00400 */ 00401 #define XOSD_COLOR_ENTRY_SIZE 4 /**< Size of each color entry in 00402 * bytes */ 00403 /*@}*/ 00404 00405 /** @name GC font unit size 00406 * @{ 00407 */ 00408 #define XOSD_FONT_BIT_TO_BYTE 8 /**< Ratio to convert font size 00409 * to byte */ 00410 /*@}*/ 00411 00412 /** @name Layer priority 00413 * @{ 00414 */ 00415 #define XOSD_LAYER_PRIORITY_0 0 /**< Priority 0 --- Lowest */ 00416 #define XOSD_LAYER_PRIORITY_1 1 /**< Priority 1 */ 00417 #define XOSD_LAYER_PRIORITY_2 2 /**< Priority 2 */ 00418 #define XOSD_LAYER_PRIORITY_3 3 /**< Priority 3 */ 00419 #define XOSD_LAYER_PRIORITY_4 4 /**< Priority 4 */ 00420 #define XOSD_LAYER_PRIORITY_5 5 /**< Priority 5 */ 00421 #define XOSD_LAYER_PRIORITY_6 6 /**< Priority 6 */ 00422 #define XOSD_LAYER_PRIORITY_7 7 /**< Priority 7 --- Highest */ 00423 /*@}*/ 00424 00425 /**************************** Type Definitions *******************************/ 00426 00427 00428 /***************** Macros (Inline Functions) Definitions *********************/ 00429 00430 /** @name Device register I/O APIs 00431 * @{ 00432 */ 00433 00434 #define XOSD_In32 XIo_In32 00435 #define XOSD_Out32 XIo_Out32 00436 00437 /*****************************************************************************/ 00438 /** 00439 * 00440 * Read the given register. 00441 * 00442 * @param BaseAddress is the base address of the device 00443 * @param RegOffset is the register offset to be read 00444 * 00445 * @return The 32-bit value of the register 00446 * 00447 * @note 00448 * C-style signature: 00449 * u32 XOSD_ReadReg(u32 BaseAddress, u32 RegOffset) 00450 * 00451 ******************************************************************************/ 00452 #define XOSD_ReadReg(BaseAddress, RegOffset) \ 00453 XOSD_In32((BaseAddress) + (RegOffset)) 00454 00455 /*****************************************************************************/ 00456 /** 00457 * 00458 * Write the given register. 00459 * 00460 * @param BaseAddress is the base address of the device 00461 * @param RegOffset is the register offset to be written 00462 * @param Data is the 32-bit value to write to the register 00463 * 00464 * @return None. 00465 * 00466 * @note 00467 * C-style signature: 00468 * void XOSD_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) 00469 * 00470 ******************************************************************************/ 00471 #define XOSD_WriteReg(BaseAddress, RegOffset, Data) \ 00472 XOSD_Out32((BaseAddress) + (RegOffset), (Data)) 00473 /*@}*/ 00474 00475 /************************** Function Prototypes ******************************/ 00476 00477 #ifdef __cplusplus 00478 } 00479 #endif 00480 00481 #endif /* end of protection macro */