TABLE OF CONTENTS

Overview
Block Diagram
External Ports
Processor
   eps7_0
Busses
   AXI_INTERCONNECT_GP0_MASTER
   AXI_INTERCONNECT_HP0_SLAVE
   AXI_INTERCONNECT_HP1_SLAVE
   AXI_INTERCONNECT_HP2_SLAVE
Peripherals
   axi_perf_mon_0
   axi_tpg_0
   axi_tpg_1
   axi_tpg_2
   axi_vdma_0
   axi_vdma_1
   axi_vdma_2
   axi_vtc_0
   osd_0
   vfbc2axi_0
   vfbc2axi_1
   vfbc2axi_2
   xsvi2axi_0
   xsvi2axi_1
   xsvi2axi_2
IP
   clock_generator_video
   csc_rgb_to_ycrcb422_0
   hdmi_interface_0
   util_bus_split_0
   zynq_addr_switch_0
   zynq_addr_switch_1
   zynq_addr_switch_2
Timing Information
Overview TOC
Resources Used
1   Processing System
4   AXI Interconnect
1   Clock Generator
1   Video Timing Controller
1   AXI Performance Monitor
3   Video Test-Pattern Generator (Engineering)
3   xsvi 2 AXI4 Streaming Bridge
3   AXI Video DMA
3   zynq_addr_switch
3   vfbc 2 AXI4 Streaming Bridge
1   Video On-Screen Display
1   Utility Bus Split
Specifics
Generated Mon Aug 20 15:52:01 2012
EDK Version 14.2
Device Family zynq
Device xc7z020clg484-1

Block Diagram TOC

BlockDiagram
External Ports TOC

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
clock_generator_video VIDEO_CLK_N I 1 VIDEO_CLK  CLK 
eps7_0 eps7_0_PS_CLK I 1 eps7_0_PS_CLK  CLK 
eps7_0 eps7_0_PS_PORB I 1 eps7_0_PS_PORB
eps7_0 eps7_0_PS_SRSTB I 1 eps7_0_PS_SRSTB
eps7_0 eps7_0_DDR_Addr IO 0:14 eps7_0_DDR_Addr
eps7_0 eps7_0_DDR_BankAddr IO 0:2 eps7_0_DDR_BankAddr
eps7_0 eps7_0_DDR_CAS_n IO 1 eps7_0_DDR_CAS_n
eps7_0 eps7_0_DDR_CKE IO 1 eps7_0_DDR_CKE
eps7_0 eps7_0_DDR_CS_n IO 1 eps7_0_DDR_CS_n
eps7_0 eps7_0_DDR_Clk IO 1 eps7_0_DDR_Clk  CLK 
eps7_0 eps7_0_DDR_Clk_n IO 1 eps7_0_DDR_Clk_n  CLK 
eps7_0 eps7_0_DDR_DM IO 0:3 eps7_0_DDR_DM
eps7_0 eps7_0_DDR_DQ IO 0:31 eps7_0_DDR_DQ
eps7_0 eps7_0_DDR_DQS IO 0:3 eps7_0_DDR_DQS
eps7_0 eps7_0_DDR_DQS_n IO 0:3 eps7_0_DDR_DQS_n
eps7_0 eps7_0_DDR_DRSTB IO 1 eps7_0_DDR_DRSTB  RESET 
eps7_0 eps7_0_DDR_ODT IO 1 eps7_0_DDR_ODT
eps7_0 eps7_0_DDR_RAS_n IO 1 eps7_0_DDR_RAS_n
eps7_0 eps7_0_DDR_VRN IO 1 eps7_0_DDR_VRN
eps7_0 eps7_0_DDR_VRP IO 1 eps7_0_DDR_VRP
eps7_0 eps7_0_MIO IO 0:53 eps7_0_MIO
eps7_0 eps7_0_DDR_WEB_pin O 1 eps7_0_DDR_WEB
hdmi_interface_0 ext_hdmi_clk O 1 ext_hdmi_clk
hdmi_interface_0 ext_hdmi_data O 0:15 ext_hdmi_data
hdmi_interface_0 ext_hdmi_de O 1 ext_hdmi_de
hdmi_interface_0 ext_hdmi_hsync O 1 ext_hdmi_hsync
hdmi_interface_0 ext_hdmi_vsync O 1 ext_hdmi_vsync
clock_generator_video VIDEO_CLK_P I 1 VIDEO_CLK  CLK 


Processors TOC

eps7_0   Processing System
Processing System wrapper for Series 7

IP Specs
Core Version Documentation
processing_system7 4.01.a IP


eps7_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 M_AXI_GP0_ACLK I 1 eps7_0_FCLK_CLK1
1 S_AXI_HP0_ACLK I 1 eps7_0_FCLK_CLK0
2 S_AXI_HP1_ACLK I 1 eps7_0_FCLK_CLK0
3 S_AXI_HP2_ACLK I 1 eps7_0_FCLK_CLK0
4 FCLK_CLKTRIG0_N I 1 net_vcc
5 FCLK_CLKTRIG1_N I 1 net_vcc
6 FCLK_CLKTRIG2_N I 1 net_vcc
7 FCLK_CLKTRIG3_N I 1 net_vcc
8 FCLK_CLK0 O 1 eps7_0_FCLK_CLK0
9 FCLK_CLK1 O 1 eps7_0_FCLK_CLK1
10 S_AXI_HP0_ARESETN O 1 eps7_0_S_AXI_HP0_ARESETN
11 S_AXI_HP1_ARESETN O 1 eps7_0_S_AXI_HP1_ARESETN
12 S_AXI_HP2_ARESETN O 1 eps7_0_S_AXI_HP2_ARESETN
13 M_AXI_GP0_ARESETN O 1 eps7_0_M_AXI_GP0_ARESETN
14 IRQ_F2P I 1 osd_0_IP2INTC_Irpt & axi_vdma_0_mm2s_introut & axi_vdma_0_s2mm_introut & axi_vdma_1_mm2s_introut & axi_vdma_1_s2mm_introut & axi_vdma_2_mm2s_introut & axi_vdma_2_s2mm_introut & axi_vtc_0_IP2INTC_Irpt
15 MIO IO 1 eps7_0_MIO
16 PS_SRSTB I 1 eps7_0_PS_SRSTB
17 PS_CLK I 1 eps7_0_PS_CLK
18 PS_PORB I 1 eps7_0_PS_PORB
19 DDR_Clk IO 1 eps7_0_DDR_Clk
20 DDR_Clk_n IO 1 eps7_0_DDR_Clk_n
21 DDR_CKE IO 1 eps7_0_DDR_CKE
22 DDR_CS_n IO 1 eps7_0_DDR_CS_n
23 DDR_RAS_n IO 1 eps7_0_DDR_RAS_n
24 DDR_CAS_n IO 1 eps7_0_DDR_CAS_n
25 DDR_WEB O 1 eps7_0_DDR_WEB
26 DDR_BankAddr IO 1 eps7_0_DDR_BankAddr
27 DDR_Addr IO 1 eps7_0_DDR_Addr
28 DDR_ODT IO 1 eps7_0_DDR_ODT
29 DDR_DRSTB IO 1 eps7_0_DDR_DRSTB
30 DDR_DQ IO 1 eps7_0_DDR_DQ
31 DDR_DM IO 1 eps7_0_DDR_DM
32 DDR_DQS IO 1 eps7_0_DDR_DQS
33 DDR_DQS_n IO 1 eps7_0_DDR_DQS_n
34 DDR_VRN IO 1 eps7_0_DDR_VRN
35 DDR_VRP IO 1 eps7_0_DDR_VRP
36 FCLK_RESET0_N O 1 FCLK_RESET_N_i
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI_GP0 MASTER AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.
S_AXI_HP0 SLAVE AXI AXI_INTERCONNECT_HP0_SLAVE 2 Peripherals.
S_AXI_HP1 SLAVE AXI AXI_INTERCONNECT_HP1_SLAVE 2 Peripherals.
S_AXI_HP2 SLAVE AXI AXI_INTERCONNECT_HP2_SLAVE 2 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EN_EMIO_CAN0 0
C_EN_EMIO_CAN1 0
C_EN_EMIO_ENET0 0
C_EN_EMIO_ENET1 0
C_EN_EMIO_GPIO 0
C_EN_EMIO_I2C0 0
C_EN_EMIO_I2C1 0
C_EN_EMIO_PJTAG 0
C_EN_EMIO_SDIO0 0
C_EN_EMIO_CD_SDIO0 0
C_EN_EMIO_WP_SDIO0 0
C_EN_EMIO_SDIO1 0
C_EN_EMIO_CD_SDIO1 0
C_EN_EMIO_WP_SDIO1 0
C_EN_EMIO_SPI0 0
C_EN_EMIO_SPI1 0
C_EN_EMIO_UART0 0
C_EN_EMIO_UART1 0
C_EN_EMIO_MODEM_UART0 0
C_EN_EMIO_MODEM_UART1 0
C_EN_EMIO_TTC0 0
C_EN_EMIO_TTC1 0
C_EN_EMIO_WDT 0
C_EN_EMIO_TRACE 0
C_USE_M_AXI_GP0 1
C_USE_M_AXI_GP1 0
C_USE_S_AXI_GP0 0
C_USE_S_AXI_GP1 0
C_USE_S_AXI_ACP 0
C_USE_S_AXI_HP0 1
C_USE_S_AXI_HP1 1
C_USE_S_AXI_HP2 1
C_USE_S_AXI_HP3 0
C_S_AXI_GP0_ENABLE_LOWOCM_DDR 0
C_S_AXI_GP1_ENABLE_LOWOCM_DDR 0
C_S_AXI_ACP_ENABLE_HIGHOCM 0
C_S_AXI_HP0_ENABLE_HIGHOCM 0
C_S_AXI_HP1_ENABLE_HIGHOCM 0
C_S_AXI_HP2_ENABLE_HIGHOCM 0
C_S_AXI_HP3_ENABLE_HIGHOCM 0
C_USE_DMA0 0
C_USE_DMA1 0
C_USE_DMA2 0
C_USE_DMA3 0
C_USE_TRACE 0
C_INCLUDE_TRACE_BUFFER 0
C_TRACE_BUFFER_FIFO_SIZE 128
USE_TRACE_DATA_EDGE_DETECTOR 0
C_TRACE_BUFFER_CLOCK_DELAY 12
C_USE_CROSS_TRIGGER 0
C_USE_CR_FABRIC 1
C_USE_AXI_FABRIC_IDLE 0
C_USE_DDR_BYPASS 0
C_USE_FABRIC_INTERRUPT 1
C_USE_PROC_EVENT_BUS 0
C_EN_EMIO_SRAM_INT 0
C_EMIO_GPIO_WIDTH 64
C_INCLUDE_ACP_TRANS_CHECK 0
C_USE_DEFAULT_ACP_USER_VAL 0
C_S_AXI_ACP_ARUSER_VAL 31
C_S_AXI_ACP_AWUSER_VAL 31
C_PS7_SI_REV PRODUCTION
C_DDR_RAM_BASEADDR 0x00000000
C_DDR_RAM_HIGHADDR 0x3FFFFFFF
C_UART0_BASEADDR 0xE0000000
C_UART0_HIGHADDR 0xE0000FFF
C_UART1_BASEADDR 0xE0001000
C_UART1_HIGHADDR 0xE0001FFF
C_I2C0_BASEADDR 0xE0004000
C_I2C0_HIGHADDR 0xE0004FFF
C_I2C1_BASEADDR 0xE0005000
C_I2C1_HIGHADDR 0xE0005FFF
C_SPI0_BASEADDR 0xE0006000
C_SPI0_HIGHADDR 0xE0006FFF
C_SPI1_BASEADDR 0xE0007000
C_SPI1_HIGHADDR 0xE0007FFF
C_CAN0_BASEADDR 0xE0008000
C_CAN0_HIGHADDR 0xE0008FFF
C_CAN1_BASEADDR 0xE0009000
C_CAN1_HIGHADDR 0xE0009FFF
C_GPIO_BASEADDR 0xE000A000
C_GPIO_HIGHADDR 0xE000AFFF
C_ENET0_BASEADDR 0xE000B000
C_ENET0_HIGHADDR 0xE000BFFF
C_ENET1_BASEADDR 0xE000C000
C_ENET1_HIGHADDR 0xE000CFFF
C_SDIO0_BASEADDR 0xE0100000
C_SDIO0_HIGHADDR 0xE0100FFF
C_SDIO1_BASEADDR 0xE0101000
C_SDIO1_HIGHADDR 0xE0101FFF
C_USB0_BASEADDR 0xE0102000
C_USB0_HIGHADDR 0xE0102FFF
C_USB1_BASEADDR 0xE0103000
C_USB1_HIGHADDR 0xE0103FFF
C_TTC0_BASEADDR 0xE0104000
C_TTC0_HIGHADDR 0xE0104FFF
C_TTC1_BASEADDR 0xE0105000
C_TTC1_HIGHADDR 0xE0105FFF
C_M_AXI_GP0_PROTOCOL AXI3
C_M_AXI_GP0_ID_WIDTH 12
C_M_AXI_GP0_ADDR_WIDTH 32
C_M_AXI_GP0_DATA_WIDTH 32
C_M_AXI_GP0_ENABLE_STATIC_REMAP 0
C_M_AXI_GP0_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP0_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP0_READ_ISSUING 8
C_M_AXI_GP1_PROTOCOL AXI3
C_M_AXI_GP1_ID_WIDTH 12
C_M_AXI_GP1_ADDR_WIDTH 32
C_M_AXI_GP1_DATA_WIDTH 32
C_M_AXI_GP1_ENABLE_STATIC_REMAP 0
C_M_AXI_GP1_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP1_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP1_READ_ISSUING 8
C_S_AXI_GP0_PROTOCOL AXI3
C_S_AXI_GP0_ID_WIDTH 6
C_S_AXI_GP0_ADDR_WIDTH 32
C_S_AXI_GP0_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE 8
C_S_AXI_GP1_PROTOCOL AXI3
 
Name Value
C_S_AXI_GP1_ID_WIDTH 6
C_S_AXI_GP1_ADDR_WIDTH 32
C_S_AXI_GP1_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE 8
C_S_AXI_ACP_PROTOCOL AXI3
C_S_AXI_ACP_ID_WIDTH 3
C_S_AXI_ACP_ADDR_WIDTH 32
C_S_AXI_ACP_DATA_WIDTH 64
C_S_AXI_ACP_SUPPORTS_USER_SIGNALS 1
C_S_AXI_ACP_ARUSER_WIDTH 5
C_S_AXI_ACP_AWUSER_WIDTH 5
C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE 8
C_S_AXI_HP0_PROTOCOL AXI3
C_S_AXI_HP0_ID_WIDTH 6
C_S_AXI_HP0_ADDR_WIDTH 32
C_S_AXI_HP0_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE 8
C_S_AXI_HP1_PROTOCOL AXI3
C_S_AXI_HP1_ID_WIDTH 6
C_S_AXI_HP1_ADDR_WIDTH 32
C_S_AXI_HP1_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE 8
C_S_AXI_HP2_PROTOCOL AXI3
C_S_AXI_HP2_ID_WIDTH 6
C_S_AXI_HP2_ADDR_WIDTH 32
C_S_AXI_HP2_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE 8
C_S_AXI_HP3_PROTOCOL AXI3
C_S_AXI_HP3_ID_WIDTH 6
C_S_AXI_HP3_ADDR_WIDTH 32
C_S_AXI_HP3_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE 8
C_S_AXI_GP0_BASEADDR 0xE0000000
C_S_AXI_GP0_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP0_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_GP1_BASEADDR 0xE0000000
C_S_AXI_GP1_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP1_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_BASEADDR 0x00000000
C_S_AXI_ACP_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_ACP_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP0_BASEADDR 0x00000000
C_S_AXI_HP0_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP1_BASEADDR 0x00000000
C_S_AXI_HP1_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP2_BASEADDR 0x00000000
C_S_AXI_HP2_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP3_BASEADDR 0x00000000
C_S_AXI_HP3_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_M_AXI_GP0_SUPPORTS_THREADS 1
C_M_AXI_GP0_THREAD_ID_WIDTH 12
C_M_AXI_GP1_SUPPORTS_THREADS 1
C_M_AXI_GP1_THREAD_ID_WIDTH 12
C_NUM_F2P_INTR_INPUTS 2
C_EN_DDR 1
C_EN_SMC 0
C_EN_QSPI 0
C_EN_CAN0 0
C_EN_CAN1 0
C_EN_ENET0 0
C_EN_ENET1 0
C_EN_GPIO 0
C_EN_I2C0 1
C_EN_I2C1 0
C_EN_PJTAG 0
C_EN_SDIO0 0
C_EN_SDIO1 0
C_EN_SPI0 0
C_EN_SPI1 0
C_EN_UART0 0
C_EN_UART1 1
C_EN_MODEM_UART0 0
C_EN_MODEM_UART1 0
C_EN_TTC0 0
C_EN_TTC1 0
C_EN_WDT 0
C_EN_TRACE 0
C_EN_USB0 0
C_EN_USB1 0
C_FCLK_CLK0_FREQ 149984985
C_FCLK_CLK1_FREQ 74992493
C_FCLK_CLK2_FREQ 199979980
C_FCLK_CLK3_FREQ 49994995
C_FCLK_CLK0_BUF TRUE
C_FCLK_CLK1_BUF TRUE
C_FCLK_CLK2_BUF TRUE
C_FCLK_CLK3_BUF TRUE
C_INTERCONNECT_S_AXI_HP0_AW_REGISTER 8
C_INTERCONNECT_S_AXI_HP0_AR_REGISTER 8
C_INTERCONNECT_S_AXI_HP0_W_REGISTER 8
C_INTERCONNECT_S_AXI_HP0_R_REGISTER 8
C_INTERCONNECT_S_AXI_HP0_B_REGISTER 8
C_INTERCONNECT_S_AXI_HP0_MASTERS axi_vdma_0.M_AXI_MM2S & axi_vdma_0.M_AXI_S2MM
C_INTERCONNECT_S_AXI_HP1_AW_REGISTER 8
C_INTERCONNECT_S_AXI_HP1_AR_REGISTER 8
C_INTERCONNECT_S_AXI_HP1_W_REGISTER 8
C_INTERCONNECT_S_AXI_HP1_R_REGISTER 8
C_INTERCONNECT_S_AXI_HP1_B_REGISTER 8
C_INTERCONNECT_S_AXI_HP1_MASTERS axi_vdma_1.M_AXI_MM2S & axi_vdma_1.M_AXI_S2MM
C_INTERCONNECT_S_AXI_HP2_AW_REGISTER 8
C_INTERCONNECT_S_AXI_HP2_AR_REGISTER 8
C_INTERCONNECT_S_AXI_HP2_W_REGISTER 8
C_INTERCONNECT_S_AXI_HP2_R_REGISTER 8
C_INTERCONNECT_S_AXI_HP2_B_REGISTER 8
C_INTERCONNECT_S_AXI_HP2_MASTERS axi_vdma_2.M_AXI_MM2S & axi_vdma_2.M_AXI_S2MM
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOC

AXI_INTERCONNECT_GP0_MASTER   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


AXI_INTERCONNECT_GP0_MASTER IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 eps7_0_FCLK_CLK1
1 INTERCONNECT_ARESETN I 1 eps7_0_M_AXI_GP0_ARESETN
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
eps7_0 MASTER M_AXI_GP0
axi_vtc_0 SLAVE S_AXI
axi_perf_mon_0 SLAVE S_AXI
axi_tpg_0 SLAVE S_AXI
axi_vdma_0 SLAVE S_AXI_LITE
axi_tpg_1 SLAVE S_AXI
axi_vdma_1 SLAVE S_AXI_LITE
axi_tpg_2 SLAVE S_AXI
axi_vdma_2 SLAVE S_AXI_LITE
osd_0 SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


AXI_INTERCONNECT_HP0_SLAVE   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


AXI_INTERCONNECT_HP0_SLAVE IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 eps7_0_FCLK_CLK0
1 INTERCONNECT_ARESETN I 1 eps7_0_S_AXI_HP0_ARESETN
2 S_AXI_ARADDR I 1 axi_interconnect_hp0_slave_S_AXI_ARADDR
3 S_AXI_AWADDR I 1 axi_interconnect_hp0_slave_S_AXI_AWADDR
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
axi_vdma_0 MASTER M_AXI_MM2S
axi_vdma_0 MASTER M_AXI_S2MM
axi_perf_mon_0 MONITOR SLOT_0_AXI
eps7_0 SLAVE S_AXI_HP0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 64
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 1
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


AXI_INTERCONNECT_HP1_SLAVE   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


AXI_INTERCONNECT_HP1_SLAVE IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 eps7_0_FCLK_CLK0
1 INTERCONNECT_ARESETN I 1 eps7_0_S_AXI_HP1_ARESETN
2 S_AXI_ARADDR I 1 axi_interconnect_hp1_slave_S_AXI_ARADDR
3 S_AXI_AWADDR I 1 axi_interconnect_hp1_slave_S_AXI_AWADDR
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
axi_vdma_1 MASTER M_AXI_MM2S
axi_vdma_1 MASTER M_AXI_S2MM
axi_perf_mon_0 MONITOR SLOT_1_AXI
eps7_0 SLAVE S_AXI_HP1


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 64
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 1
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


AXI_INTERCONNECT_HP2_SLAVE   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


AXI_INTERCONNECT_HP2_SLAVE IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 eps7_0_FCLK_CLK0
1 INTERCONNECT_ARESETN I 1 eps7_0_S_AXI_HP2_ARESETN
2 S_AXI_ARADDR I 1 axi_interconnect_hp2_slave_S_AXI_ARADDR
3 S_AXI_AWADDR I 1 axi_interconnect_hp2_slave_S_AXI_AWADDR
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
axi_vdma_2 MASTER M_AXI_MM2S
axi_vdma_2 MASTER M_AXI_S2MM
axi_perf_mon_0 MONITOR SLOT_2_AXI
eps7_0 SLAVE S_AXI_HP2


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 64
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 1
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOC

axi_perf_mon_0   AXI Performance Monitor
Measures performance of AXI4-based system

IP Specs
Core Version Documentation
axi_perf_mon 2.00.a IP


axi_perf_mon_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 eps7_0_FCLK_CLK1
1 CORE_ACLK I 1 eps7_0_FCLK_CLK0
2 CORE_ARESETN I 1 eps7_0_S_AXI_HP0_ARESETN
3 Capture_Event I 1 0b0
4 Reset_Event I 1 0b0
5 SLOT_0_AXI_ACLK I 1 eps7_0_FCLK_CLK0
6 SLOT_1_AXI_ACLK I 1 eps7_0_FCLK_CLK0
7 SLOT_2_AXI_ACLK I 1 eps7_0_FCLK_CLK0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SLOT_0_AXI MONITOR AXI AXI_INTERCONNECT_HP0_SLAVE 2 Peripherals.
SLOT_1_AXI MONITOR AXI AXI_INTERCONNECT_HP1_SLAVE 2 Peripherals.
SLOT_2_AXI MONITOR AXI AXI_INTERCONNECT_HP2_SLAVE 2 Peripherals.
S_AXI SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex7
C_INSTANCE axi_perf_mon_inst
C_BASEADDR 0x41000000
C_HIGHADDR 0x4100FFFF
C_S_AXI_ADDR_WIDTH 16
C_S_AXI_DATA_WIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
C_NUM_MONITOR_SLOTS 3
C_ENABLE_EVENT_COUNT 1
C_NUM_OF_COUNTERS 2
C_METRIC_COUNT_WIDTH 32
C_GLOBAL_COUNT_WIDTH 32
C_METRICS_SAMPLE_COUNT_WIDTH 32
C_MAX_OUTSTAND_DEPTH 1
C_MAX_REORDER_DEPTH 1
C_SLOT_0_AXI_ADDR_WIDTH 32
C_SLOT_0_AXI_DATA_WIDTH 64
C_SLOT_0_AXI_ID_WIDTH 1
C_SLOT_0_AXI_PROTOCOL AXI4MM
C_SLOT_0_AXIS_TDATA_WIDTH 32
C_SLOT_0_AXIS_TID_WIDTH 1
C_SLOT_0_AXIS_TDEST_WIDTH 1
C_SLOT_0_AXIS_TUSER_WIDTH 1
C_SLOT_0_FIFO_ENABLE 0
C_SLOT_1_AXI_ADDR_WIDTH 32
C_SLOT_1_AXI_DATA_WIDTH 64
C_SLOT_1_AXI_ID_WIDTH 1
C_SLOT_1_AXI_PROTOCOL AXI4MM
C_SLOT_1_AXIS_TDATA_WIDTH 32
C_SLOT_1_AXIS_TID_WIDTH 1
C_SLOT_1_AXIS_TDEST_WIDTH 1
C_SLOT_1_AXIS_TUSER_WIDTH 1
C_SLOT_1_FIFO_ENABLE 0
C_SLOT_2_AXI_ADDR_WIDTH 32
C_SLOT_2_AXI_DATA_WIDTH 64
C_SLOT_2_AXI_ID_WIDTH 1
C_SLOT_2_AXI_PROTOCOL AXI4MM
C_SLOT_2_AXIS_TDATA_WIDTH 32
C_SLOT_2_AXIS_TID_WIDTH 1
C_SLOT_2_AXIS_TDEST_WIDTH 1
C_SLOT_2_AXIS_TUSER_WIDTH 1
C_SLOT_2_FIFO_ENABLE 0
C_SLOT_3_AXI_ADDR_WIDTH 32
C_SLOT_3_AXI_DATA_WIDTH 32
C_SLOT_3_AXI_ID_WIDTH 1
C_SLOT_3_AXI_PROTOCOL AXI4MM
C_SLOT_3_AXIS_TDATA_WIDTH 32
C_SLOT_3_AXIS_TID_WIDTH 1
C_SLOT_3_AXIS_TDEST_WIDTH 1
C_SLOT_3_AXIS_TUSER_WIDTH 1
C_SLOT_3_FIFO_ENABLE 1
C_SLOT_4_AXI_ADDR_WIDTH 32
 
Name Value
C_SLOT_4_AXI_DATA_WIDTH 32
C_SLOT_4_AXI_ID_WIDTH 1
C_SLOT_4_AXI_PROTOCOL AXI4MM
C_SLOT_4_AXIS_TDATA_WIDTH 32
C_SLOT_4_AXIS_TID_WIDTH 1
C_SLOT_4_AXIS_TDEST_WIDTH 1
C_SLOT_4_AXIS_TUSER_WIDTH 1
C_SLOT_4_FIFO_ENABLE 1
C_SLOT_5_AXI_ADDR_WIDTH 32
C_SLOT_5_AXI_DATA_WIDTH 32
C_SLOT_5_AXI_ID_WIDTH 1
C_SLOT_5_AXI_PROTOCOL AXI4MM
C_SLOT_5_AXIS_TDATA_WIDTH 32
C_SLOT_5_AXIS_TID_WIDTH 1
C_SLOT_5_AXIS_TDEST_WIDTH 1
C_SLOT_5_AXIS_TUSER_WIDTH 1
C_SLOT_5_FIFO_ENABLE 1
C_SLOT_6_AXI_ADDR_WIDTH 32
C_SLOT_6_AXI_DATA_WIDTH 32
C_SLOT_6_AXI_ID_WIDTH 1
C_SLOT_6_AXI_PROTOCOL AXI4MM
C_SLOT_6_AXIS_TDATA_WIDTH 32
C_SLOT_6_AXIS_TID_WIDTH 1
C_SLOT_6_AXIS_TDEST_WIDTH 1
C_SLOT_6_AXIS_TUSER_WIDTH 1
C_SLOT_6_FIFO_ENABLE 1
C_SLOT_7_AXI_ADDR_WIDTH 32
C_SLOT_7_AXI_DATA_WIDTH 32
C_SLOT_7_AXI_ID_WIDTH 1
C_SLOT_7_AXI_PROTOCOL AXI4MM
C_SLOT_7_AXIS_TDATA_WIDTH 32
C_SLOT_7_AXIS_TID_WIDTH 1
C_SLOT_7_AXIS_TDEST_WIDTH 1
C_SLOT_7_AXIS_TUSER_WIDTH 1
C_SLOT_7_FIFO_ENABLE 1
C_MON_SLOTS_AXI_ID_MAX_WIDTH 6
C_MON_SLOTS_AXI_ADDR_MAX_WIDTH 32
C_MON_SLOTS_AXI_DATA_MAX_WIDTH 64
C_MON_SLOTS_AXIS_TDATA_MAX_WIDTH 32
C_MON_SLOTS_AXIS_TID_MAX_WIDTH 1
C_MON_SLOTS_AXIS_TDEST_MAX_WIDTH 1
C_MON_SLOTS_AXIS_TUSER_MAX_WIDTH 1
C_REG_ALL_MONITOR_SIGNALS 0
C_EXT_EVENT0_FIFO_ENABLE 1
C_EXT_EVENT1_FIFO_ENABLE 1
C_ENABLE_EVENT_LOG 1
C_FIFO_AXIS_DEPTH 32
C_FIFO_AXIS_TDATA_WIDTH 256
C_FIFO_AXIS_TID_WIDTH 1
C_AXI4LITE_CORE_CLK_ASYNC 1
C_HAVE_SAMPLED_METRIC_CNT 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_tpg_0   Video Test-Pattern Generator (Engineering)


IP Specs
Core Version
axi_tpg 2.00.a


axi_tpg_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 eps7_0_FCLK_CLK1
1 clk I 1 video_clk_s
2 video_data_in I 1 net_vcc
3 hsync_in I 1 axi_vtc_0_XSVI_OUT_hsync
4 vsync_in I 1 axi_vtc_0_XSVI_OUT_vsync
5 hblank_in I 1 axi_vtc_0_XSVI_OUT_hblank
6 vblank_in I 1 axi_vtc_0_XSVI_OUT_vblank
7 active_video_in I 1 axi_vtc_0_XSVI_OUT_active_video
8 video_data_out O 1 axi_tpg_0_video_data
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
XSVI_TPG_OUT INITIATOR XSVI tpg_0_XSVI_TPG_OUT xsvi2axi_0
S_AXI SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4LITE
C_S_AXI_ID_WIDTH 4
C_BASEADDR 0x5EE00000
C_HIGHADDR 0x5EE0FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_S_AXI_CLK_FREQ_HZ 100000000
C_FAMILY virtex5
C_CHROMA_FORMAT 0
C_DATA_WIDTH 8
C_NUM_CHANNELS 3
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_tpg_1   Video Test-Pattern Generator (Engineering)


IP Specs
Core Version
axi_tpg 2.00.a


axi_tpg_1 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 eps7_0_FCLK_CLK1
1 clk I 1 video_clk_s
2 video_data_in I 1 net_vcc
3 hsync_in I 1 axi_vtc_0_XSVI_OUT_hsync
4 vsync_in I 1 axi_vtc_0_XSVI_OUT_vsync
5 hblank_in I 1 axi_vtc_0_XSVI_OUT_hblank
6 vblank_in I 1 axi_vtc_0_XSVI_OUT_vblank
7 active_video_in I 1 axi_vtc_0_XSVI_OUT_active_video
8 video_data_out O 1 axi_tpg_1_video_data
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
XSVI_TPG_OUT INITIATOR XSVI tpg_1_XSVI_TPG_OUT xsvi2axi_1
S_AXI SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4LITE
C_S_AXI_ID_WIDTH 4
C_BASEADDR 0x5EE10000
C_HIGHADDR 0x5EE1FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_S_AXI_CLK_FREQ_HZ 100000000
C_FAMILY virtex5
C_CHROMA_FORMAT 0
C_DATA_WIDTH 8
C_NUM_CHANNELS 3
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_tpg_2   Video Test-Pattern Generator (Engineering)


IP Specs
Core Version
axi_tpg 2.00.a


axi_tpg_2 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 eps7_0_FCLK_CLK1
1 clk I 1 video_clk_s
2 video_data_in I 1 net_vcc
3 hsync_in I 1 axi_vtc_0_XSVI_OUT_hsync
4 vsync_in I 1 axi_vtc_0_XSVI_OUT_vsync
5 hblank_in I 1 axi_vtc_0_XSVI_OUT_hblank
6 vblank_in I 1 axi_vtc_0_XSVI_OUT_vblank
7 active_video_in I 1 axi_vtc_0_XSVI_OUT_active_video
8 video_data_out O 1 axi_tpg_2_video_data
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
XSVI_TPG_OUT INITIATOR XSVI tpg_2_XSVI_TPG_OUT xsvi2axi_2
S_AXI SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4LITE
C_S_AXI_ID_WIDTH 4
C_BASEADDR 0x5EE20000
C_HIGHADDR 0x5EE2FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_S_AXI_CLK_FREQ_HZ 100000000
C_FAMILY virtex5
C_CHROMA_FORMAT 0
C_DATA_WIDTH 8
C_NUM_CHANNELS 3
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_vdma_0   AXI Video DMA
MemoryMap to/from Stream Video Direct Memory Access for AXI

IP Specs
Core Version Documentation
axi_vdma 5.02.a IP


axi_vdma_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 s_axi_lite_aclk I 1 eps7_0_FCLK_CLK1
1 m_axi_mm2s_aclk I 1 eps7_0_FCLK_CLK0
2 m_axi_s2mm_aclk I 1 eps7_0_FCLK_CLK0
3 m_axis_mm2s_aclk I 1 video_clk_s
4 s_axis_s2mm_aclk I 1 video_clk_s
5 mm2s_fsync I 1 axi_vtc_0_fsync
6 s2mm_fsync I 1 axi_vtc_0_fsync
7 s2mm_frame_ptr_out O 1 axi_vdma_0_s2mm_frame_ptr_out
8 mm2s_frame_ptr_in I 1 axi_vdma_0_s2mm_frame_ptr_out
9 mm2s_frame_ptr_out O 1 axi_vdma_0_mm2s_frame_ptr_out
10 mm2s_introut O 1 axi_vdma_0_mm2s_introut
11 s2mm_introut O 1 axi_vdma_0_s2mm_introut
12 s2mm_prmry_reset_out_n O 1 axi_vdma_0_s2mm_prmry_0_reset_out_n
13 m_axi_mm2s_araddr O 1 axi_interconnect_hp0_slave_S_ARADDR
14 m_axi_s2mm_awaddr O 1 axi_interconnect_hp0_slave_S_AWADDR
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXIS_MM2S INITIATOR AXIS axi_vdma_0_M_AXIS_MM2S vfbc2axi_0
M_AXI_MM2S MASTER AXI AXI_INTERCONNECT_HP0_SLAVE 2 Peripherals.
M_AXI_S2MM MASTER AXI AXI_INTERCONNECT_HP0_SLAVE 2 Peripherals.
S_AXI_LITE SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.
S_AXIS_S2MM TARGET AXIS xsvi2axi_0_M_AXIS_S2MM xsvi2axi_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_LITE_ADDR_WIDTH 9
C_S_AXI_LITE_DATA_WIDTH 32
C_DLYTMR_RESOLUTION 125
C_PRMRY_IS_ACLK_ASYNC 1
C_M_AXI_SG_ADDR_WIDTH 32
C_M_AXI_SG_DATA_WIDTH 32
C_NUM_FSTORES 3
C_USE_FSYNC 1
C_FLUSH_ON_FSYNC 1
C_INCLUDE_SG 0
C_INCLUDE_INTERNAL_GENLOCK 0
C_ENABLE_VIDPRMTR_READS 1
C_INCLUDE_MM2S 1
C_M_AXI_MM2S_DATA_WIDTH 32
C_M_AXIS_MM2S_TDATA_WIDTH 32
C_INCLUDE_MM2S_DRE 0
C_INCLUDE_MM2S_SF 0
C_MM2S_SOF_ENABLE 0
C_MM2S_MAX_BURST_LENGTH 32
C_MM2S_GENLOCK_MODE 1
C_MM2S_GENLOCK_NUM_MASTERS 1
C_MM2S_GENLOCK_REPEAT_EN 0
C_MM2S_LINEBUFFER_DEPTH 8192
C_MM2S_LINEBUFFER_THRESH 8160
C_M_AXI_MM2S_ADDR_WIDTH 32
C_M_AXIS_MM2S_TUSER_BITS 1
C_INCLUDE_S2MM 1
C_M_AXI_S2MM_DATA_WIDTH 32
C_S_AXIS_S2MM_TDATA_WIDTH 32
C_INCLUDE_S2MM_DRE 0
C_INCLUDE_S2MM_SF 0
C_S2MM_SOF_ENABLE 0
C_S2MM_MAX_BURST_LENGTH 32
C_S2MM_GENLOCK_MODE 0
C_S2MM_GENLOCK_NUM_MASTERS 1
C_S2MM_GENLOCK_REPEAT_EN 0
C_S2MM_LINEBUFFER_DEPTH 8192
C_S2MM_LINEBUFFER_THRESH 8160
C_M_AXI_S2MM_ADDR_WIDTH 32
 
Name Value
C_S_AXIS_S2MM_TUSER_BITS 1
C_FAMILY virtex6
C_INSTANCE axi_vdma
C_BASEADDR 0x40000000
C_HIGHADDR 0x4000FFFF
C_S_AXI_LITE_PROTOCOL AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ 1
C_S_AXI_LITE_SUPPORTS_WRITE 1
C_M_AXI_SG_PROTOCOL AXI4
C_M_AXI_SG_SUPPORTS_THREADS 0
C_M_AXI_SG_THREAD_ID_WIDTH 1
C_M_AXI_SG_SUPPORTS_NARROW_BURST 0
C_M_AXI_SG_SUPPORTS_READ 1
C_M_AXI_SG_SUPPORTS_WRITE 0
C_M_AXI_MM2S_PROTOCOL AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS 0
C_M_AXI_MM2S_THREAD_ID_WIDTH 1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST 0
C_M_AXI_MM2S_SUPPORTS_READ 1
C_M_AXI_MM2S_SUPPORTS_WRITE 0
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH 512
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING 2
C_M_AXI_S2MM_PROTOCOL AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS 0
C_M_AXI_S2MM_THREAD_ID_WIDTH 1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST 0
C_M_AXI_S2MM_SUPPORTS_WRITE 1
C_M_AXI_S2MM_SUPPORTS_READ 0
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH 512
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING 2
C_M_AXIS_MM2S_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_S_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER 8
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER 8
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DELAY 1
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DELAY 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_vdma_1   AXI Video DMA
MemoryMap to/from Stream Video Direct Memory Access for AXI

IP Specs
Core Version Documentation
axi_vdma 5.02.a IP


axi_vdma_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 s_axi_lite_aclk I 1 eps7_0_FCLK_CLK1
1 m_axi_mm2s_aclk I 1 eps7_0_FCLK_CLK0
2 m_axi_s2mm_aclk I 1 eps7_0_FCLK_CLK0
3 m_axis_mm2s_aclk I 1 video_clk_s
4 s_axis_s2mm_aclk I 1 video_clk_s
5 mm2s_fsync I 1 axi_vtc_0_fsync
6 s2mm_fsync I 1 axi_vtc_0_fsync
7 s2mm_frame_ptr_out O 1 axi_vdma_1_s2mm_frame_ptr_out
8 mm2s_frame_ptr_in I 1 axi_vdma_1_s2mm_frame_ptr_out
9 mm2s_frame_ptr_out O 1 axi_vdma_1_mm2s_frame_ptr_out
10 mm2s_introut O 1 axi_vdma_1_mm2s_introut
11 s2mm_introut O 1 axi_vdma_1_s2mm_introut
12 s2mm_prmry_reset_out_n O 1 axi_vdma_1_s2mm_prmry_0_reset_out_n
13 m_axi_mm2s_araddr O 1 axi_interconnect_hp1_slave_S_ARADDR
14 m_axi_s2mm_awaddr O 1 axi_interconnect_hp1_slave_S_AWADDR
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXIS_MM2S INITIATOR AXIS axi_vdma_1_M_AXIS_MM2S vfbc2axi_1
M_AXI_MM2S MASTER AXI AXI_INTERCONNECT_HP1_SLAVE 2 Peripherals.
M_AXI_S2MM MASTER AXI AXI_INTERCONNECT_HP1_SLAVE 2 Peripherals.
S_AXI_LITE SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.
S_AXIS_S2MM TARGET AXIS xsvi2axi_1_M_AXIS_S2MM xsvi2axi_1


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_LITE_ADDR_WIDTH 9
C_S_AXI_LITE_DATA_WIDTH 32
C_DLYTMR_RESOLUTION 125
C_PRMRY_IS_ACLK_ASYNC 1
C_M_AXI_SG_ADDR_WIDTH 32
C_M_AXI_SG_DATA_WIDTH 32
C_NUM_FSTORES 3
C_USE_FSYNC 1
C_FLUSH_ON_FSYNC 1
C_INCLUDE_SG 0
C_INCLUDE_INTERNAL_GENLOCK 0
C_ENABLE_VIDPRMTR_READS 1
C_INCLUDE_MM2S 1
C_M_AXI_MM2S_DATA_WIDTH 32
C_M_AXIS_MM2S_TDATA_WIDTH 32
C_INCLUDE_MM2S_DRE 0
C_INCLUDE_MM2S_SF 0
C_MM2S_SOF_ENABLE 0
C_MM2S_MAX_BURST_LENGTH 32
C_MM2S_GENLOCK_MODE 1
C_MM2S_GENLOCK_NUM_MASTERS 1
C_MM2S_GENLOCK_REPEAT_EN 0
C_MM2S_LINEBUFFER_DEPTH 8192
C_MM2S_LINEBUFFER_THRESH 8160
C_M_AXI_MM2S_ADDR_WIDTH 32
C_M_AXIS_MM2S_TUSER_BITS 1
C_INCLUDE_S2MM 1
C_M_AXI_S2MM_DATA_WIDTH 32
C_S_AXIS_S2MM_TDATA_WIDTH 32
C_INCLUDE_S2MM_DRE 0
C_INCLUDE_S2MM_SF 0
C_S2MM_SOF_ENABLE 0
C_S2MM_MAX_BURST_LENGTH 32
C_S2MM_GENLOCK_MODE 0
C_S2MM_GENLOCK_NUM_MASTERS 1
C_S2MM_GENLOCK_REPEAT_EN 0
C_S2MM_LINEBUFFER_DEPTH 8192
C_S2MM_LINEBUFFER_THRESH 8160
C_M_AXI_S2MM_ADDR_WIDTH 32
 
Name Value
C_S_AXIS_S2MM_TUSER_BITS 1
C_FAMILY virtex6
C_INSTANCE axi_vdma
C_BASEADDR 0x40010000
C_HIGHADDR 0x4001FFFF
C_S_AXI_LITE_PROTOCOL AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ 1
C_S_AXI_LITE_SUPPORTS_WRITE 1
C_M_AXI_SG_PROTOCOL AXI4
C_M_AXI_SG_SUPPORTS_THREADS 0
C_M_AXI_SG_THREAD_ID_WIDTH 1
C_M_AXI_SG_SUPPORTS_NARROW_BURST 0
C_M_AXI_SG_SUPPORTS_READ 1
C_M_AXI_SG_SUPPORTS_WRITE 0
C_M_AXI_MM2S_PROTOCOL AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS 0
C_M_AXI_MM2S_THREAD_ID_WIDTH 1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST 0
C_M_AXI_MM2S_SUPPORTS_READ 1
C_M_AXI_MM2S_SUPPORTS_WRITE 0
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH 512
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING 2
C_M_AXI_S2MM_PROTOCOL AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS 0
C_M_AXI_S2MM_THREAD_ID_WIDTH 1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST 0
C_M_AXI_S2MM_SUPPORTS_WRITE 1
C_M_AXI_S2MM_SUPPORTS_READ 0
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH 512
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING 2
C_M_AXIS_MM2S_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_S_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER 8
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER 8
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DELAY 1
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DELAY 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_vdma_2   AXI Video DMA
MemoryMap to/from Stream Video Direct Memory Access for AXI

IP Specs
Core Version Documentation
axi_vdma 5.02.a IP


axi_vdma_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 s_axi_lite_aclk I 1 eps7_0_FCLK_CLK1
1 m_axi_mm2s_aclk I 1 eps7_0_FCLK_CLK0
2 m_axi_s2mm_aclk I 1 eps7_0_FCLK_CLK0
3 m_axis_mm2s_aclk I 1 video_clk_s
4 s_axis_s2mm_aclk I 1 video_clk_s
5 mm2s_fsync I 1 axi_vtc_0_fsync
6 s2mm_fsync I 1 axi_vtc_0_fsync
7 s2mm_frame_ptr_out O 1 axi_vdma_2_s2mm_frame_ptr_out
8 mm2s_frame_ptr_out O 1 axi_vdma_2_mm2s_frame_ptr_out
9 mm2s_frame_ptr_in I 1 axi_vdma_2_s2mm_frame_ptr_out
10 mm2s_introut O 1 axi_vdma_2_mm2s_introut
11 s2mm_introut O 1 axi_vdma_2_s2mm_introut
12 s2mm_prmry_reset_out_n O 1 axi_vdma_2_s2mm_prmry_0_reset_out_n
13 m_axi_mm2s_araddr O 1 axi_interconnect_hp2_slave_S_ARADDR
14 m_axi_s2mm_awaddr O 1 axi_interconnect_hp2_slave_S_AWADDR
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXIS_MM2S INITIATOR AXIS axi_vdma_2_M_AXIS_MM2S vfbc2axi_2
M_AXI_MM2S MASTER AXI AXI_INTERCONNECT_HP2_SLAVE 2 Peripherals.
M_AXI_S2MM MASTER AXI AXI_INTERCONNECT_HP2_SLAVE 2 Peripherals.
S_AXI_LITE SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.
S_AXIS_S2MM TARGET AXIS xsvi2axi_2_M_AXIS_S2MM xsvi2axi_2


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_LITE_ADDR_WIDTH 9
C_S_AXI_LITE_DATA_WIDTH 32
C_DLYTMR_RESOLUTION 125
C_PRMRY_IS_ACLK_ASYNC 1
C_M_AXI_SG_ADDR_WIDTH 32
C_M_AXI_SG_DATA_WIDTH 32
C_NUM_FSTORES 3
C_USE_FSYNC 1
C_FLUSH_ON_FSYNC 1
C_INCLUDE_SG 0
C_INCLUDE_INTERNAL_GENLOCK 0
C_ENABLE_VIDPRMTR_READS 1
C_INCLUDE_MM2S 1
C_M_AXI_MM2S_DATA_WIDTH 32
C_M_AXIS_MM2S_TDATA_WIDTH 32
C_INCLUDE_MM2S_DRE 0
C_INCLUDE_MM2S_SF 0
C_MM2S_SOF_ENABLE 0
C_MM2S_MAX_BURST_LENGTH 32
C_MM2S_GENLOCK_MODE 1
C_MM2S_GENLOCK_NUM_MASTERS 1
C_MM2S_GENLOCK_REPEAT_EN 0
C_MM2S_LINEBUFFER_DEPTH 8192
C_MM2S_LINEBUFFER_THRESH 8160
C_M_AXI_MM2S_ADDR_WIDTH 32
C_M_AXIS_MM2S_TUSER_BITS 1
C_INCLUDE_S2MM 1
C_M_AXI_S2MM_DATA_WIDTH 32
C_S_AXIS_S2MM_TDATA_WIDTH 32
C_INCLUDE_S2MM_DRE 0
C_INCLUDE_S2MM_SF 0
C_S2MM_SOF_ENABLE 0
C_S2MM_MAX_BURST_LENGTH 32
C_S2MM_GENLOCK_MODE 0
C_S2MM_GENLOCK_NUM_MASTERS 1
C_S2MM_GENLOCK_REPEAT_EN 0
C_S2MM_LINEBUFFER_DEPTH 8192
C_S2MM_LINEBUFFER_THRESH 8160
C_M_AXI_S2MM_ADDR_WIDTH 32
 
Name Value
C_S_AXIS_S2MM_TUSER_BITS 1
C_FAMILY virtex6
C_INSTANCE axi_vdma
C_BASEADDR 0x40020000
C_HIGHADDR 0x4002FFFF
C_S_AXI_LITE_PROTOCOL AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ 1
C_S_AXI_LITE_SUPPORTS_WRITE 1
C_M_AXI_SG_PROTOCOL AXI4
C_M_AXI_SG_SUPPORTS_THREADS 0
C_M_AXI_SG_THREAD_ID_WIDTH 1
C_M_AXI_SG_SUPPORTS_NARROW_BURST 0
C_M_AXI_SG_SUPPORTS_READ 1
C_M_AXI_SG_SUPPORTS_WRITE 0
C_M_AXI_MM2S_PROTOCOL AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS 0
C_M_AXI_MM2S_THREAD_ID_WIDTH 1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST 0
C_M_AXI_MM2S_SUPPORTS_READ 1
C_M_AXI_MM2S_SUPPORTS_WRITE 0
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH 512
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING 2
C_M_AXI_S2MM_PROTOCOL AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS 0
C_M_AXI_S2MM_THREAD_ID_WIDTH 1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST 0
C_M_AXI_S2MM_SUPPORTS_WRITE 1
C_M_AXI_S2MM_SUPPORTS_READ 0
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH 512
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING 2
C_M_AXIS_MM2S_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_S_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_B_REGISTER 8
C_INTERCONNECT_M_AXI_MM2S_R_REGISTER 8
C_INTERCONNECT_M_AXI_S2MM_W_REGISTER 8
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DELAY 1
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DELAY 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_vtc_0   Video Timing Controller
The Xilinx Video Timing Controller LogiCORE(TM) is a general purpose video timing generator and detector. Automatic detection of horizontal and vertical front and back porches

IP Specs
Core Version
axi_vtc 3.00.a


axi_vtc_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 video_clk_in I 1 video_clk_s
1 fsync O 1 axi_vtc_0_fsync
2 vblank_out O 1 axi_vtc_0_XSVI_OUT_vblank
3 vsync_out O 1 axi_vtc_0_XSVI_OUT_vsync
4 hblank_out O 1 axi_vtc_0_XSVI_OUT_hblank
5 hsync_out O 1 axi_vtc_0_XSVI_OUT_hsync
6 active_video_out O 1 axi_vtc_0_XSVI_OUT_active_video
7 active_chroma_out O 1 axi_vtc_0_XSVI_OUT_active_chroma_out
8 IP2INTC_Irpt O 1 axi_vtc_0_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DET_AUTO_SWITCH 1
C_MAX_PIXELS 4096
C_MAX_LINES 4096
C_NUM_FSYNCS 1
C_DETECT_EN 0
C_GENERATE_EN 1
C_DET_HSYNC_EN 1
C_DET_VSYNC_EN 1
C_DET_HBLANK_EN 0
C_DET_VBLANK_EN 0
C_DET_AVIDEO_EN 1
C_DET_ACHROMA_EN 0
C_GEN_HSYNC_EN 1
 
Name Value
C_GEN_VSYNC_EN 1
C_GEN_HBLANK_EN 1
C_GEN_VBLANK_EN 1
C_GEN_AVIDEO_EN 1
C_GEN_ACHROMA_EN 1
C_S_AXI_PROTOCOL AXI4LITE
C_S_AXI_ID_WIDTH 4
C_BASEADDR 0x53800000
C_HIGHADDR 0x5380FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_CLK_FREQ_HZ 100000000
C_FAMILY virtex7
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


osd_0   Video On-Screen Display
The Xilinx On-Screen Display LogiCORE provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. Support for up to eight layers using a combination of external video inputs (from frame buffer) and internal graphics controllers (including text generators) is provided. Supported image sizes up to 4kx4k with YUVa 4:4:4 or 4:2:2 and RGBa image formats up to 1080p 60fps. The core is programmable through a comprehensive register interface for setting and controlling screen size

IP Specs
Core Version
axi_osd 2.00.a


osd_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 eps7_0_FCLK_CLK1
1 clk I 1 video_clk_s
2 IP2INTC_Irpt O 1 osd_0_IP2INTC_Irpt
3 vsync_out O 1 csc_ycrcb422_to_rgb_0_XSVI_OUT_vsync
4 hsync_out O 1 csc_ycrcb422_to_rgb_0_XSVI_OUT_hsync
5 active_video_out O 1 csc_ycrcb422_to_rgb_0_XSVI_OUT_active_video
6 video_data_out O 1 osd_rgb_out
7 hsync_in I 1 axi_vtc_0_XSVI_OUT_hsync
8 vsync_in I 1 axi_vtc_0_XSVI_OUT_vsync
9 hblank_in I 1 axi_vtc_0_XSVI_OUT_hblank
10 vblank_in I 1 axi_vtc_0_XSVI_OUT_vblank
11 active_chroma_in I 1 axi_vtc_0_XSVI_OUT_active_chroma_out
12 active_video_in I 1 axi_vtc_0_XSVI_OUT_active_video
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
XIL_RD0_VFBC INITIATOR XIL_VFBC osd_0_XIL_RD0_VFBC vfbc2axi_0
XIL_RD1_VFBC INITIATOR XIL_VFBC osd_0_XIL_RD1_VFBC vfbc2axi_1
XIL_RD2_VFBC INITIATOR XIL_VFBC osd_0_XIL_RD2_VFBC vfbc2axi_2
S_AXI SLAVE AXI AXI_INTERCONNECT_GP0_MASTER 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_DATA_WIDTH 8
C_NUM_LAYERS 3
C_NUM_DATA_CHANNELS 3
C_SCREEN_WIDTH 1280
C_READ_FIFO_LATENCY 1
C_ALPHA_CHANNEL_EN 0
C_OUTPUT_MODE 1
C_VFBC_RD_DATA_WIDTH 32
C_VFBC_WD_DATA_WIDTH 16
C_LAYER0_TYPE 2
C_LAYER1_TYPE 2
C_LAYER2_TYPE 2
C_LAYER3_TYPE 2
C_LAYER4_TYPE 2
C_LAYER5_TYPE 2
C_LAYER6_TYPE 2
C_LAYER7_TYPE 2
C_LAYER0_IMEM_SIZE 48
C_LAYER0_INS_BOX_EN 1
C_LAYER0_INS_LINE_EN 0
C_LAYER0_INS_TEXT_EN 1
C_LAYER0_CLUT_SIZE 16
C_LAYER0_CLUT_MEMTYPE 2
C_LAYER0_FONT_NUM_CHARS 96
C_LAYER0_FONT_WIDTH 8
C_LAYER0_FONT_HEIGHT 8
C_LAYER0_FONT_BPP 1
C_LAYER0_FONT_ASCII_OFFSET 32
C_LAYER0_TEXT_NUM_STRINGS 8
C_LAYER0_TEXT_MAX_STRING_LENGTH 32
C_LAYER1_IMEM_SIZE 48
C_LAYER1_INS_BOX_EN 1
C_LAYER1_INS_LINE_EN 0
C_LAYER1_INS_TEXT_EN 1
C_LAYER1_CLUT_SIZE 16
C_LAYER1_CLUT_MEMTYPE 2
C_LAYER1_FONT_NUM_CHARS 96
C_LAYER1_FONT_WIDTH 8
C_LAYER1_FONT_HEIGHT 8
C_LAYER1_FONT_BPP 1
C_LAYER1_FONT_ASCII_OFFSET 32
C_LAYER1_TEXT_NUM_STRINGS 8
C_LAYER1_TEXT_MAX_STRING_LENGTH 32
C_LAYER2_IMEM_SIZE 48
C_LAYER2_INS_BOX_EN 1
C_LAYER2_INS_LINE_EN 0
C_LAYER2_INS_TEXT_EN 1
C_LAYER2_CLUT_SIZE 16
C_LAYER2_CLUT_MEMTYPE 2
C_LAYER2_FONT_NUM_CHARS 96
C_LAYER2_FONT_WIDTH 8
C_LAYER2_FONT_HEIGHT 8
C_LAYER2_FONT_BPP 1
C_LAYER2_FONT_ASCII_OFFSET 32
C_LAYER2_TEXT_NUM_STRINGS 8
C_LAYER2_TEXT_MAX_STRING_LENGTH 32
C_LAYER3_IMEM_SIZE 48
C_LAYER3_INS_BOX_EN 1
C_LAYER3_INS_LINE_EN 0
C_LAYER3_INS_TEXT_EN 1
C_LAYER3_CLUT_SIZE 16
C_LAYER3_CLUT_MEMTYPE 2
C_LAYER3_FONT_NUM_CHARS 96
C_LAYER3_FONT_WIDTH 8
C_LAYER3_FONT_HEIGHT 8
 
Name Value
C_LAYER3_FONT_BPP 1
C_LAYER3_FONT_ASCII_OFFSET 32
C_LAYER3_TEXT_NUM_STRINGS 8
C_LAYER3_TEXT_MAX_STRING_LENGTH 32
C_LAYER4_IMEM_SIZE 48
C_LAYER4_INS_BOX_EN 1
C_LAYER4_INS_LINE_EN 0
C_LAYER4_INS_TEXT_EN 1
C_LAYER4_CLUT_SIZE 16
C_LAYER4_CLUT_MEMTYPE 2
C_LAYER4_FONT_NUM_CHARS 96
C_LAYER4_FONT_WIDTH 8
C_LAYER4_FONT_HEIGHT 8
C_LAYER4_FONT_BPP 1
C_LAYER4_FONT_ASCII_OFFSET 32
C_LAYER4_TEXT_NUM_STRINGS 8
C_LAYER4_TEXT_MAX_STRING_LENGTH 32
C_LAYER5_IMEM_SIZE 48
C_LAYER5_INS_BOX_EN 1
C_LAYER5_INS_LINE_EN 0
C_LAYER5_INS_TEXT_EN 1
C_LAYER5_CLUT_SIZE 16
C_LAYER5_CLUT_MEMTYPE 2
C_LAYER5_FONT_NUM_CHARS 96
C_LAYER5_FONT_WIDTH 8
C_LAYER5_FONT_HEIGHT 8
C_LAYER5_FONT_BPP 1
C_LAYER5_FONT_ASCII_OFFSET 32
C_LAYER5_TEXT_NUM_STRINGS 8
C_LAYER5_TEXT_MAX_STRING_LENGTH 32
C_LAYER6_IMEM_SIZE 48
C_LAYER6_INS_BOX_EN 1
C_LAYER6_INS_LINE_EN 0
C_LAYER6_INS_TEXT_EN 1
C_LAYER6_CLUT_SIZE 16
C_LAYER6_CLUT_MEMTYPE 2
C_LAYER6_FONT_NUM_CHARS 96
C_LAYER6_FONT_WIDTH 8
C_LAYER6_FONT_HEIGHT 8
C_LAYER6_FONT_BPP 1
C_LAYER6_FONT_ASCII_OFFSET 32
C_LAYER6_TEXT_NUM_STRINGS 8
C_LAYER6_TEXT_MAX_STRING_LENGTH 32
C_LAYER7_IMEM_SIZE 48
C_LAYER7_INS_BOX_EN 1
C_LAYER7_INS_LINE_EN 0
C_LAYER7_INS_TEXT_EN 1
C_LAYER7_CLUT_SIZE 16
C_LAYER7_CLUT_MEMTYPE 2
C_LAYER7_FONT_NUM_CHARS 96
C_LAYER7_FONT_WIDTH 8
C_LAYER7_FONT_HEIGHT 8
C_LAYER7_FONT_BPP 1
C_LAYER7_FONT_ASCII_OFFSET 32
C_LAYER7_TEXT_NUM_STRINGS 8
C_LAYER7_TEXT_MAX_STRING_LENGTH 32
C_S_AXI_PROTOCOL AXI4LITE
C_S_AXI_ID_WIDTH 4
C_BASEADDR 0x43A00000
C_HIGHADDR 0x43A0FFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_CLK_FREQ_HZ 100000000
C_FAMILY virtex5
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


vfbc2axi_0   vfbc 2 AXI4 Streaming Bridge
vfbc 2 AXI4 Streaming Bridge

IP Specs
Core Version
vfbc2axi 1.00.e


vfbc2axi_0 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXIS_MM2S TARGET AXIS axi_vdma_0_M_AXIS_MM2S axi_vdma_0
XIL_VFBC TARGET XIL_VFBC osd_0_XIL_RD0_VFBC osd_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_M_AXIS_S2MM_TDATA_WIDTH 32
C_S_AXIS_MM2S_TDATA_WIDTH 32
C_M_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_S_AXIS_MM2S_PROTOCOL XIL_AXI_STREAM_VID_DATA
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


vfbc2axi_1   vfbc 2 AXI4 Streaming Bridge
vfbc 2 AXI4 Streaming Bridge

IP Specs
Core Version
vfbc2axi 1.00.e


vfbc2axi_1 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXIS_MM2S TARGET AXIS axi_vdma_1_M_AXIS_MM2S axi_vdma_1
XIL_VFBC TARGET XIL_VFBC osd_0_XIL_RD1_VFBC osd_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_M_AXIS_S2MM_TDATA_WIDTH 32
C_S_AXIS_MM2S_TDATA_WIDTH 32
C_M_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_S_AXIS_MM2S_PROTOCOL XIL_AXI_STREAM_VID_DATA
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


vfbc2axi_2   vfbc 2 AXI4 Streaming Bridge
vfbc 2 AXI4 Streaming Bridge

IP Specs
Core Version
vfbc2axi 1.00.e


vfbc2axi_2 IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXIS_MM2S TARGET AXIS axi_vdma_2_M_AXIS_MM2S axi_vdma_2
XIL_VFBC TARGET XIL_VFBC osd_0_XIL_RD2_VFBC osd_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_M_AXIS_S2MM_TDATA_WIDTH 32
C_S_AXIS_MM2S_TDATA_WIDTH 32
C_M_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
C_S_AXIS_MM2S_PROTOCOL XIL_AXI_STREAM_VID_DATA
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xsvi2axi_0   xsvi 2 AXI4 Streaming Bridge
xsvi 2 AXI4 Streaming Bridge

IP Specs
Core Version
xsvi2axi 1.01.c


xsvi2axi_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 m_axis_aresetn I 1 axi_vdma_0_s2mm_prmry_0_reset_out_n
1 video_clk I 1 video_clk_s
2 video_data I 1 0b00000000 & axi_tpg_0_video_data
3 fsync_in I 1 axi_vtc_0_fsync
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXIS_S2MM INITIATOR AXIS xsvi2axi_0_M_AXIS_S2MM axi_vdma_0
XSVI TARGET XSVI tpg_0_XSVI_TPG_OUT axi_tpg_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_M_AXIS_S2MM_TDATA_WIDTH 32
C_M_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xsvi2axi_1   xsvi 2 AXI4 Streaming Bridge
xsvi 2 AXI4 Streaming Bridge

IP Specs
Core Version
xsvi2axi 1.01.c


xsvi2axi_1 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 m_axis_aresetn I 1 axi_vdma_1_s2mm_prmry_0_reset_out_n
1 video_clk I 1 video_clk_s
2 video_data I 1 0b00000000 & axi_tpg_1_video_data
3 fsync_in I 1 axi_vtc_0_fsync
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXIS_S2MM INITIATOR AXIS xsvi2axi_1_M_AXIS_S2MM axi_vdma_1
XSVI TARGET XSVI tpg_1_XSVI_TPG_OUT axi_tpg_1


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_M_AXIS_S2MM_TDATA_WIDTH 32
C_M_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xsvi2axi_2   xsvi 2 AXI4 Streaming Bridge
xsvi 2 AXI4 Streaming Bridge

IP Specs
Core Version
xsvi2axi 1.01.c


xsvi2axi_2 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 m_axis_aresetn I 1 axi_vdma_2_s2mm_prmry_0_reset_out_n
1 video_clk I 1 video_clk_s
2 video_data I 1 0b00000000 & axi_tpg_2_video_data
3 fsync_in I 1 axi_vtc_0_fsync
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXIS_S2MM INITIATOR AXIS xsvi2axi_2_M_AXIS_S2MM axi_vdma_2
XSVI TARGET XSVI tpg_2_XSVI_TPG_OUT axi_tpg_2


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_M_AXIS_S2MM_TDATA_WIDTH 32
C_M_AXIS_S2MM_PROTOCOL XIL_AXI_STREAM_VID_DATA
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOC

clock_generator_video   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_video IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CLKOUT0 O 1 video_clk_s
1 CLKIN I 1 VIDEO_CLK
2 LOCKED O 1 proc_sys_reset_0_Dcm_locked
3 RST I 1 FCLK_RESET_N_i


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 148500000
C_CLKOUT0_FREQ 148500000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP MMCM0
C_CLKOUT0_BUF TRUE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 0
C_CLKOUT1_PHASE 0
C_CLKOUT1_GROUP NONE
C_CLKOUT1_BUF TRUE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 0
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 0
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 0
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP NONE
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 0
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


csc_rgb_to_ycrcb422_0


IP Specs
Core Version
csc_rgb_to_ycrcb422 1.01.b


csc_rgb_to_ycrcb422_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 vblank_i I 1 0b0
1 hblank_i I 1 0b0
2 vsync_i I 1 csc_ycrcb422_to_rgb_0_XSVI_OUT_vsync
3 hsync_i I 1 csc_ycrcb422_to_rgb_0_XSVI_OUT_hsync
4 active_video_i I 1 csc_ycrcb422_to_rgb_0_XSVI_OUT_active_video
5 video_data_i I 1 osd_rgb_out
6 vsync_o O 1 i_vsync_out
7 hsync_o O 1 i_hsync_out
8 active_video_o O 1 i_active_video_out
9 video_data_o O 1 i_YCrCb422_data_out
10 clk I 1 video_clk_s
11 ce I 1 net_vcc


Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


hdmi_interface_0
Handles connectivity between XSVI Interface to KC705 HDMI Connectivity (on-board)

IP Specs
Core Version
hdmi_interface 1.01.a


hdmi_interface_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 clk I 1 video_clk_s
1 ce I 1 net_vcc
2 de_i I 1 i_active_video_out
3 vsync_i I 1 i_vsync_out
4 hsync_i I 1 i_hsync_out
5 Y_i I 1 i_Y_data
6 CrCb_i I 1 i_CrCb_data
7 hdmi_de O 1 ext_hdmi_de
8 hdmi_vsync O 1 ext_hdmi_vsync
9 hdmi_hsync O 1 ext_hdmi_hsync
10 hdmi_data O 1 ext_hdmi_data
11 hdmi_clk O 1 ext_hdmi_clk


Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


util_bus_split_0   Utility Bus Split
Bus splitting primitive

IP Specs
Core Version Documentation
util_bus_split 1.00.a IP


util_bus_split_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Sig I 1 i_YCrCb422_data_out
1 Out1 O 1 i_CrCb_data
2 Out2 O 1 i_Y_data


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SIZE_IN 16
C_LEFT_POS 0
C_SPLIT 8
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


zynq_addr_switch_0   zynq_addr_switch


IP Specs
Core Version
zynq_addr_switch 1.00.a


zynq_addr_switch_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 M0_AXI_AWADDR I 1 0b00000000000000000000000000000000
1 M0_AXI_ARADDR I 1 axi_interconnect_hp0_slave_S_ARADDR
2 M1_AXI_AWADDR I 1 axi_interconnect_hp0_slave_S_AWADDR
3 M1_AXI_ARADDR I 1 0b00000000000000000000000000000000
4 S_AXI_AWADDR O 1 axi_interconnect_hp0_slave_S_AXI_AWADDR
5 S_AXI_ARADDR O 1 axi_interconnect_hp0_slave_S_AXI_ARADDR


Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


zynq_addr_switch_1   zynq_addr_switch


IP Specs
Core Version
zynq_addr_switch 1.00.a


zynq_addr_switch_1 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 M0_AXI_AWADDR I 1 0b00000000000000000000000000000000
1 M0_AXI_ARADDR I 1 axi_interconnect_hp1_slave_S_ARADDR
2 M1_AXI_AWADDR I 1 axi_interconnect_hp1_slave_S_AWADDR
3 M1_AXI_ARADDR I 1 0b00000000000000000000000000000000
4 S_AXI_AWADDR O 1 axi_interconnect_hp1_slave_S_AXI_AWADDR
5 S_AXI_ARADDR O 1 axi_interconnect_hp1_slave_S_AXI_ARADDR


Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


zynq_addr_switch_2   zynq_addr_switch


IP Specs
Core Version
zynq_addr_switch 1.00.a


zynq_addr_switch_2 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 M0_AXI_AWADDR I 1 0b00000000000000000000000000000000
1 M0_AXI_ARADDR I 1 axi_interconnect_hp2_slave_S_ARADDR
2 M1_AXI_AWADDR I 1 axi_interconnect_hp2_slave_S_AWADDR
3 M1_AXI_ARADDR I 1 0b00000000000000000000000000000000
4 S_AXI_AWADDR O 1 axi_interconnect_hp2_slave_S_AXI_AWADDR
5 S_AXI_ARADDR O 1 axi_interconnect_hp2_slave_S_AXI_ARADDR


Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOC


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.