EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB sys_rst_pin I 1 sys_rst_s  RESET  1A fpga_0_FLASH_16Mx8_Mem_DQ_pin IO 0:7 fpga_0_FLASH_16Mx8_Mem_DQ 2A fpga_0_FLASH_16Mx8_Mem_CEN_pin O 0:0 fpga_0_FLASH_16Mx8_Mem_CEN 3A fpga_0_FLASH_16Mx8_Mem_OEN_pin O 1 fpga_0_FLASH_16Mx8_Mem_OEN 4A fpga_0_FLASH_16Mx8_Mem_WEN_pin O 1 fpga_0_FLASH_16Mx8_Mem_WEN 5B fpga_0_FLASH_16Mx8_Mem_A_pin O 8:31 fpga_0_FLASH_16Mx8_Mem_A 6C fpga_0_LEDs_1Bit_GPIO_d_out_pin O 0:0 fpga_0_LEDs_1Bit_GPIO_d_out 7D fpga_0_RS232_DTE_RX_pin I 1 fpga_0_RS232_DTE_RX 8D fpga_0_RS232_DTE_TX_pin O 1 fpga_0_RS232_DTE_TX 9E sys_clk_pin I 1 dcm_clk_s  CLK  10E fpga_0_FLASH_16Mx8_emc_ben_gnd_pin O 1 net_gnd