Board and Kit Documentation

This getting started guide is designed to help you quickly and efficiently develop embedded systems using a fully integrated development platform.

This user guide provides a detailed description of each component and peripheral available on the ML501 Evaluation Platform. The ML501 board is a low-cost, entry-level platform for evaluation of Virtex®-5 LX FPGAs.

This user guide introduces several designs that demonstrate Virtex®-5 device features using the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms. The provided designs include processing systems based on the embedded PowerPC® 440 processor block, the MicroBlaze™ soft processor, the integrated Tri-mode Ethernet MAC, and the RocketIO™ GTP or GTX transceiver.

Design File(s):

• ML507 designs
• ML506 designs
• ML505 designs

This notice is to communicate that Xilinx is discontinuing certain Development Systems Products.

This application note describes how the standard network performance suite Netperf is used to measure XPS LL TEMAC performance with MontaVista Linux 4.0.

Design File(s):

• xapp1127.zip

To communicate that Xilinx is discontinuing certain Development Systems Products.

This guide documents the PHY daughter card for use with Xilinx ML32x Development Platforms.

This guide provides instructions for designing and accelerating the development of new products, and provides an excellent medium for consumer-oriented wireless and multimedia video applications.

Design File(s):

• Spartan_3A_SDSP_Board_Schematic.zip

This user guide describes how to use the FMC-Video daughter card, which is a part of the Spartan®-3A DSP Video Starter Kit (VSK) for firmware development. The user guide includes descriptions of the hardware, software tools, files, and test designs that are used.

Design File(s):

• ug458_1.zip
• ug458_2.zip
• FMC_Video_IO_Card_Schematic.zip

The ML505/ML506/ML507 Getting Started Tutorial provides step-by-step instructions for setting up and using the Virtex®-5 ML505, ML506, and ML507 Evaluation Platforms. These boards come with a number of pre-installed demonstrations. This tutorial guides you through these demonstrations and provides instructions to run them on the ML50x boards.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs

This user guide describes the Virtex™-5 FPGA ML555 Development Kit for PCI and PCI Express designs.

This guide provides information about how to use the Video Starter Kit (VSK) to begin experimenting with video processing using the Spartan®-3A DSP family of FPGAs.

This quick start guide provides a brief overview of the Spartan®-3A DSP FPGA Video Starter Kit (VSK) and how to run a set of pre-defined demonstration designs.

This user guide provides information and guidelines for using the Spartan®-3A DSP FPGA Video Starter Kit (VSK), a development platform consisting of the Spartan-3A DSP 3400A Development Platform, the FMC-Video daughter card, and a VGA camera.

Design File(s):

• ug456_11_4_vsk_v3_0.zip

To communicate that Xilinx is discontinuing certain Development Systems products relates to LogiCORE™ IP, Image Processing Pipeline and Xilinx® Development Systems Kits and Boards Products on While Supplies Last.

The Virtex®-6 FPGA Connectivity Kit provides a comprehensive, high-performance Connectivity Development and Demonstration platform using the Virtex-6 family for high-bandwidth and high-performance applications in multiple market segments. This guide describes the contents of the Virtex-6 FPGA Connectivity Kit and gives instructions on how to start developing connectivity systems.

Design File(s):

• ug664.zip

This application note describes how to interface a Fujitsu MB86064 digital-to-analog converter (DAC) with parallel low-voltage differential signaling (LVDS) inputs to a Virtex®-5 FPGA utilizing the dedicated I/O functions of the FPGA family.

Design File(s):

• xapp873.zip

The purpose is to describe the functionality and contents of the Spartan®-3A DSP Starter Platform from Xilinx. This document includes instructions for operating the board and descriptions of the hardware features.

Design File(s):

• Sp3ADSP Rev D GERBERS.zip
• Sp3A-DSP-1800A-Starter-Schematic-Rev1.pdf
• Sp3ADSP_Rev_1_(Rev_D_board)_GERBERS_PDF.zip
• Spartan-3A DSP 1800A Starter UCF
• Spartan-3A DSP 1800A Starter BOM

The Virtex®-4 ML461 Memory Interfaces Tool Kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex®-4 LX FPGA family.

Design File(s):

• ML461 MIG Reference Design Files

This user guide describes the Virtex®-5 FPGA ML561 Memory Interfaces Development Board, which is the heart of the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit. The tool kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex-5 LXT Platform.

Design File(s):

• ML561 MIG Reference Design Files

This document describes the FPGA broadcast mezzanine card (FMC card), which provides interfaces for professional broadcast audio and video equipment.

This user guide describes the features and operation of the Virtex®-5 LXT and FXT FPGAs series of RocketIO™ characterization platforms, which includes the ML521, ML523, and ML525 boards.

This guide describes the contents of the Spartan®-6 FPGA Connectivity Kit and provides instructions on how to start developing connectivity systems using GTP transceivers and LogiCORE™ IP in Spartan-6 FPGAs.

Design File(s):

• ug665.zip

The Virtex®-6 FPGA Connectivity Kit provides a comprehensive, high-performance Connectivity Development and Demonstration platform using the Virtex-6 family for high-bandwidth and high-performance applications in multiple market segments. This guide describes the contents of the Virtex-6 FPGA Connectivity Kit and gives instructions on how to start developing connectivity systems.

This user guide showcases various features of the Virtex®-5 FXT FPGA ML507 development board. It describes the hardware platform, the HelloWorld software application, and the BlueCat Linux images.

Design File(s):

• ug511_mb_emb_ref.zip
• ug511_ppc440_emb_ref.zip

This tutorial helps you get started using the ML401/ML402/ML403/ML405 evaluation platforms. These boards come with a number of pre-installed demonstration programs. This document guides you through these demonstrations and explains how to run them.

Design File(s):

• ML402 Reference Designs
• ML403 Reference Designs

This document describes the FPGA Mezzanine Card (FMC) XM101 LVDS QSE card.

This guide describes the contents of the Spartan®-6 FPGA Connectivity Kit and provides instructions on how to start developing connectivity systems using GTP transceivers and LogiCORE™ IP in Spartan-6 FPGAs.

This guide describes the contents of the Spartan®-6 FPGA Connectivity Kit and provides instructions on how to start developing connectivity systems using GTP transceivers and LogiCORE™ IP in Spartan-6 FPGAs.

The Virtex®-6 FPGA Connectivity Kit provides a comprehensive, high-performance Connectivity Development and Demonstration platform using the Virtex-6 family for high-bandwidth and high-performance applications in multiple market segments. This guide describes the contents of the Virtex-6 FPGA Connectivity Kit and gives instructions on how to start developing connectivity systems.

This user guide details a targeted reference design developed for the connectivity domain on a Spartan®-6 FPGA. The aim is to accelerate the design cycle and enable FPGA designers to spend less time developing the infrastructure of an application and more time creating a unique value-add design.

Design File(s):

• ug665.zip

This user guide details a targeted reference design developed for the connectivity domain on a Virtex®-6 FPGA. The aim is to accelerate the design cycle and enable FPGA designers to spend less time developing the infrastructure of an application and more time creating a unique, value-added design.

Design File(s):

• ug664.zip

Instructions for redeeming Xilinx software and IP licenses using the new voucher process. These instructions should be used in combination with the Getting Started Guide: Installing the ISE® Software section.

This document describes the features and operation of the Virtex™-II Pro X MK322 and MK325 prototype and demonstration boards.

This user guide describes the components and operation of the Spartan®-3E FPGA Starter Kit Board. The Starter Kit provides a low-cost, easy-to-use development and evaluation platform for Spartan-3E FPGA designs.

Design File(s):

• S3E_Starter_Schematic.pdf
• Reference Designs
• s3e_starter_gerbers.pdf
• S3E_SK_BOM_RevD.xls

This user guide details a targeted reference design developed for the connectivity domain on a Virtex®-6 FPGA. The aim is to accelerate the design cycle and enable FPGA designers to spend less time developing the infrastructure of an application and more time creating a unique, value-added design.

This is the Spartan®-3A DSP S3D1800A Getting Started Guide.

Design File(s):

• Sp3ADSP Rev D GERBERS.zip
• Sp3A-DSP-1800A-Starter-Schematic-Rev1.pdf
• Sp3ADSP_Rev_1_(Rev_D_board)_GERBERS_PDF.zip
• Spartan-3A DSP 1800A Starter UCF
• Spartan-3A DSP 1800A Starter BOM

This user guide describes the features and operation of the Virtex®-5 LX FPGA prototype platform and provides instructions to configure chains of FPGAs and serial PROMs.

The ML50x boards enable designers to investigate and experiment with features of Virtex®-5 FPGAs. This user guide describes the features and operation of the ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms.

Design File(s):

• ML507 docs
• ML506 docs
• ML505 docs

This manual accompanies the ML510 Embedded Development Platform and contains information about the ML510 hardware and software tools. The ML510 offers designers a versatile Virtex®-5 FXT platform for rapid prototyping and system verification.

Design File(s):

• ML510 docs

This document describes the FPGA Mezzanine Card (FMC) debug mezzanine card (HWFMC-DBG-G) for use with supported Xilinx boards.

This document provides a procedure for setting up the ML623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 13.2.

This user guide details a targeted reference design developed for the connectivity domain on a Virtex®-6 FPGA. The aim is to accelerate the design cycle and enable FPGA designers to spend less time developing the infrastructure of an application and more time creating a unique, value-added design.

The Virtex®-6 FPGA Connectivity Kit provides a comprehensive, high-performance Connectivity Development and Demonstration platform using the Virtex-6 family for high-bandwidth and high-performance applications in multiple market segments. This guide describes the contents of the Virtex-6 FPGA Connectivity Kit and gives instructions on how to start developing connectivity systems.

To communicate that Xilinx is discontinuing certain Development Systems Products.

To communicate that Xilinx is discontinuing certain Development Systems Products.

Tutorial for CoolRunner™-II Evaluation Board.

Design File(s):

• ML605 BIST Design Files (12.3 C)

Design File(s):

• ML605 FMC XM104 IBERT Design Files (12.3 CES)

Design File(s):

• ML605 GTX IBERT Design Files (12.3 CES)

Design File(s):

• ML605 GTX IBERT Design Files (12.3 C)

Design File(s):

• ML605 MIG Design Files (12.3 CES)

Design File(s):

• ML605 MultiBoot Design Files (12.3 CES)

Design File(s):

• ML605 MultiBoot Design Files (12.3 C)

XTP053 describes stand-alone applications for the SP601 evaluation board.

Design File(s):

• Design file for xtp053.pdf.

Design File(s):

• ML605 PCIe Gen1 x8 Design Files (12.3 C)

Design File(s):

• ML605 PCIe Gen2 x4 Design Files (12.3 CES)

Design File(s):

• ML605 Restoring Flash Contents Design Files (12.3 CES)

Design File(s):

• ML605 Restoring Flash Contents Design Files (12.3 C)

Design File(s):

• ML605 System Monitor Design Files (12.3 CES)

Design File(s):

• ML605 System Monitor Design Files (12.3 C)

Create a PCIe® x8 Gen1 Design for the ML605 using CORE Generator™.

This document describes how to create a PCIe® x4 Gen2 for the ML605 using CORE Generator™.

This document describes using MIG to create a DDR3 memory design for the ML605.

This document describes a simple System Monitor for the ML605.

Explains how to run, compile, and program the BIST Flash Application for the ML605.

Design File(s):

• SP601 Standalone Applications Design Files (13.1 C)

Design File(s):

• SP601 Standalone Applications Design Files (12.3 C)

Design File(s):

• SP601 Standalone Applications Design Files (12.3 CES)

Design File(s):

• SP601 BIST Design Files (12.3 CES)

Design File(s):

• SP601 BIST Design Files (12.3 C)

Design File(s):

• SP605 BIST Design Files (12.3 C)

Design File(s):

• SP605 BIST Design Files (12.3 CES)

This tutorial and design supports the Spartan®-6 FPGA SP605 Evaluation Board.

This tutorial and design supports the Spartan®-6 FPGA SP605 Evaluation Board.

This document provides information for getting started with the Virtex®-6 FPGA ML605 Embedded Kit.

The Spartan®-6 FPGA SP605 Evaluation Kit enables hardware and software developers to create or evaluate designs targeting the XC6SLX45T-3FGG484 Spartan-6 FPGA.

Design File(s):

• SP605 BRD Design Files (13.3 C)

XTP042 describes the base system reference design (BSRD) flash application for the SP601 evaluation board.

Design File(s):

• Design file for xtp042.pdf.

The Spartan®-6 FPGA SP601 Evaluation Kit enables hardware and software developers to create or evaluate designs targeting the XC6SLX16-CS324 Spartan-6 FPGA.

Design File(s):

• SP601 BRD Design Files (13.3 C)

This guide provides information for getting started with the Spartan®-6 FPGA SP605 Embedded Kit.

This guide provides information for getting started with the Xilinx Spartan®-6 FPGA SP605 Embedded Development Kit.

Design File(s):

• SP605 Embedded Kit Reference Designs and Documentation Files, ISE Software v11.4

This user guide accompanies the Spartan®-6 FPGA SP605 Evaluation Board and contains information about the SP605 hardware and software tools.

Design File(s):

• SP601 BIST Design Files (13.1 C)

Setup for SP605 Evaluation Board

This is a PDF of the ML605 printed-circuit board.

Design File(s):

• ML605 PCIe Gen1 x8 Design Files (12.3 CES)

This guide provides information for getting started with the Xilinx Virtex®-6 FPGA ML605 Evaluation Kit.

Design File(s):

• ML605 Embedded Kit Reference Designs and Documentation Files, ISE Software v11.4

Design File(s):

• ML605 MIG Design Files (12.3 C)

This manual accompanies the Virtex®-6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools.

This document describes Creating and Using a ChipScope™ IBERT Design with the ML605 board.

Design File(s):

• ML605 FMC XM104 IBERT Design Files (12.3 C)

XTP052 is the PDF of the ML605 rev D schematics.

Setup for ML605 Evaluation Board

Design File(s):

• SP601 MultiBoot Design Files (12.3 C)

Design File(s):

• SP601 MultiBoot Design Files (12.3 CES)

Design File(s):

• SP605 MultiBoot Design Files (12.3 C)

This user guide introduces several designs that demonstrate Spartan®-6 FPGA features using the SP601 evaluation board.

Design File(s):

• SP605 MultiBoot Design Files (12.3 CES)

This tutorial and design supports the Spartan®-6 FPGA SP605 Evaluation Board.

Design File(s):

• SP605 PCIe Gen1 x1 Design Files (12.3 C)

Design File(s):

• SP605 PCIe Gen1 x1 Design Files (12.3 CES)

This document describes the basic setup, features, and operation of the ML628 Virtex®-6 FPGA GTX and GTH transceiver characterization board. The ML628 board provides the hardware environment for characterizing and evaluating the GTX and GTH transceivers available on the Virtex-6 XC6VHX380T-2C FPGA in the FFG1923 package.

This document provides a procedure for setting up the ML628 Virtex®-6 FPGA GTX and GTH Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration.

Design File(s):

• SP601 Restoring Flash Contents Design Files (13.1 C)

Design File(s):

• SP601 Restoring Flash Contents Design Files (12.3 C)

Design File(s):

• SP601 Restoring Flash Contents Design Files (12.3 CES)

This user guide introduces designs that demonstrate Virtex®-6 FPGA device features using the ML605 evaluation board.

This document describes how to restore the Flash Memory and Compact Flash of the ML605 to factory defaults.

Design File(s):

• ML605 PCIe Gen2 x4 Design Files (12.3 C)

This tutorial and design supports the Spartan®-6 FPGA SP605 Evaluation Board.

Design File(s):

• SP605 MIG Design Files (12.3 C)

Design File(s):

• SP605 MIG Design Files (12.3 CES)

This user guide introduces several designs that demonstrate Spartan®-6 FPGA features using the SP601 evaluation board. The provided designs include processing systems based on the MultiBoot and the Xilinx® Memory Interface Generator for the Spartan-6 FPGA.

Design File(s):

• SP601 BRD Design Files (13.1 C)

XTP040 is a tutorial for restoring the flash contents on the SP601 evaluation board to the original factory settings.

Design File(s):

• Design File for xtp040.pdf

This tutorial and design supports the Spartan®-6 FPGA SP605 Evaluation Board.

This document describes the basic setup, features, and operation of the ML623 Virtex®-6 FPGA GTX transceiver characterization board. The ML623 board provides the hardware environment for characterizing and evaluating the GTX transceivers available on the Virtex-6 XC6VLX240T FPGA.

This document provides a procedure for setting up the ML623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 12.1.

This document provides a procedure for setting up the ML623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 12.3.

This document provides a procedure for setting up the ML623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 13.1.

Design File(s):

• SP605 GTP IBERT Design Files (12.3 C)

Design File(s):

• SP605 GTP IBERT Design Creation PDF (12.3 CES)

Design File(s):

• SP605 Standalone Applications Design Files (12.3 CES)

This is the PDF for the SP601 schematics. The PCB files (Allegro 15.x) and schematic source files (Viewdraw) are accessible from the link below.

This document provides a procedure for setting up the ML623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 11.5.

This document provides a procedure for setting up the SP623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 12.1.

This document provides a procedure for setting up the SP623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 12.3.

This document provides a procedure for setting up the SP623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 13.1.

This document provides a procedure for setting up the SP623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 13.2.

This document provides a procedure for setting up the SP623 Virtex®-6 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using ISE® software version 11.4.

This document describes the basic setup, features, and operation of the SP623 Spartan®-6 FPGA GTP transceiver characterization board. The SP623 board provides the hardware environment for characterizing and evaluating the GTP transceivers available on the Spartan-6 XC6SLX150T-3FGG676 FPGA.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System: http://www.xilinx.com/support/myalerts.

This Design Advisory covers the Virtex-6 FPGA Broadcast Connectivity Kit including critical issues with the reference design delivered with the kit.

This application note demonstrates how to create a basic DDR3 MPMC design using the ISE® Design Suite Logic Edition tools, including Project Navigator (ProjNav) and the CORE Generator™ tool.

Design File(s):

• xapp739_axi_mpmc.zip

Design File(s):

• ML605 BIST Design Files (12.3 CES)

This document describes known issues for the ML605 evaluation board.

This document describes known issues for the SP605 evaluation kit printed circuit board Assembly.

This document describes the basic setup, features, and operation of the ML630 Virtex®-6 FPGA HXT Optical Transmission Network (OTN evaluation board.

UG533 introduces the Virtex®-6 FPGA ML605 board features, provides instructions setting up the hardware, and provides step-by-step procedures for verifying the ML605 board functionality.