Characterization Reports

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-4 RocketIO™ MGT.

This report communicates the conditions, results, and procedural methods used to achieve a quantified test of interoperation between a Virtex™-5 GTP transceiver and a Virtex-II Pro RocketIO™ MGT.

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Serial ATA Generation 2 (3 Gb/s) specification.

This report describes the electrical performance characterization testing of the Virtex™-5 RocketIO™ GTP transceiver against the Fibre Channel specifications.

This report describes the electrical performance characterization testing of the Virtex™-5 GTP transceiver against the Common Public Radio Interface (CPRI) specifications.

This report describes the electrical performance characterization testing of the GTP transceiver against the PCI Express specifications.

This report describes the electrical performance characterization testing of the GTP transceiver against the OC-48 specifications.

This report describes the electrical performance characterization testing of the Virtex®-5 FPGA RocketIO™ GTP transceiver against the 10 Gb Attachment Unit Interface (XAUI) specification.

This report describes the electrical performance characterization testing of the GTP transceiver against the Gigabit Ethernet serial protocol standards.

This report documents the results of characterization performed on the Virtex™-5 Clock Management Tile(CMT) that combines two enhanced Digital Clock Managers (DCMs) with one Phase-Locked Loop (PLL), and clocking resources.

This characterization report provides FPGA characterization results for Virtex®-5 LXT and SXT RocketIO™ GTP transceivers across specified process, voltage, and temperature (PVT) conditions.

This characterization report provides design verification and characterization results for Virtex™-4 FX RocketIO™ Multi-Gigabit Transceivers (MGTs) using process, voltage, and temperature (PVT) conditions.

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against OIF-CEI-02.0, "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps I/O".

This report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against the 2.0 PCI Express® specifications.

This document serves as a general characterization report for the Virtex®-5 FPGA RocketIO™ GTX transceiver. The measurement results in this report provide a detailed view of the behavior of the transceiver across process, voltage, and temperature corners.

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against International Telecommunication Union Telecommunication Standardization Sector (ITU-T) Recommendation G.2851, The control of jitter and wander within the optical transport network (OTN).

This characterization report compares the electrical performance of the Virtex®-5 FPGA RocketIO™ GTX transceiver against the GR-253-CORE standard.

Aerospace and Defense Bumping Supplier Change: Virtex®-4QV Space-Grade Devices Using Ceramic Flip-Chip Column Grid, Qualification Report

This document is a general characterization report for the Virtex®-6 FPGA GTX transceiver. The measurement results provide a detailed view of the behavior of the transceiver across process, voltage, and temperature (PVT) corners.

Compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against OIF-CEI-02.0, Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6+ Gb/s and 11+ Gb/s I/O.

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the PCI Express® Revision 2.0 specifications published in the PCI Express Base Specification, Revision 2.1 and the PCI Express Card Electromechanical Specification, Revision 2.0.

This protocol compatibility report compares the physical layer (PHY) electrical performance of the Virtex®-6 FPGA GTX transceiver against the Common Public Radio Interface (CPRI) specification, v4.1.

This protocol characterization summary report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the 10 Gb Attachment Unit Interface (XAUI) specifications.

This characterization report compares the electrical performance of the Spartan®-6 FPGA GTP transceiver against the PCI Express® Revision 1.1 specifications published in the PCI Express Base Specification, Revision 1.1 and the PCI Express Card Electromechanical Specification, Revision 1.1. All testing for this report is based on a line rate of 2.5 Gb/s across voltage, temperature, and worst-case transceiver performance corners.

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) Recommendation G.8251.

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTH transceivers against OIF-CEI-02.0, Common Electrical I/O (CEI)—Electrical and Jitter Interoperability agreements for 6 Gb/s and 11 Gb/s I/O and IEEE Std 802.3ba-2010 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications.

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTH transceiver against the SFP+ (SFI) SFF-8431 electrical specification.

Report summarizes the results of the reliability stress tests performed to qualify copper wire for use in wire-bonded packages.