Configuration Hardware

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

The Tagalyzer is a diagnostic tool that helps debug long JTAG boundary scan chains. It can be modified to adapt to a wide variety of different testing situations, and is made from a single XC9536 CPLD. It can be used to debug JTAG chains made up of any manufacturer's parts. The Tagalyzer can be expanded to support arbitrarily long boundary scan chains and adapted to change its functionality as needed.

This document provides an overview of Hardware Co-Simulation in System Generator for DSP from a performance perspective, and provides information to help reduce long simulation run times.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This document provides a brief description of the Xilinx bitstream compression algorithm based on the LZ77 scheme. FPGA configuration files can be compressed by Xilinx-developed software to reduce memory storage requirements. Compressed configuration files can be stored in a high-density System ACE MPM FPGA configuration controller. The System ACE MPM controller decompresses the files and shifts the original configuration data to the target FPGAs.