CoolRunner-II

This application note shows how a Xilinx® CoolRunner™-II CPLD can be used as a simple logical switch that can quickly and reliably select between different MPEG video sources.

This application note documents using a Xilinx® CPLD as a motor controller.

This application note shows how to connect an Intel Processor to a hard-disk drive.

This Application Note presents a method for doubling the frequency resolution of counter and timer applications using CoolRunner™-II.

This appnote shows how to use a CoolRunner™-II to interface with multiple SD cards.

Using CoolRunner™-II CPLDs with standard chipsets.

Uses CoolRunner™-II to control dot matrix LCD module. Includes design file.

This application note describes how to drive LEDs using Xilinx CPLDs.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

This application note presents a design of a port expander that fits into a CoolRunner™-II XC2C32A device. The port expander is SMBus and I2C compatible.

This application note demonstrates how to use a CoolRunner™-II CPLD as a Level Translator.

Checklist application note giving best practice CPLD design methodology.

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

This application note provides a functional description of Verilog source code for a keypad scanner.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note helps guide designers in fitting designs into the smallest possible CPLD devices.

Describes the bahavior of CPLDs during power up.

This application note provides a good guideline on PCB pad pattern design and assembling of QFN packages for optimal reliability and quality. This is only a guideline, and users are encouraged to perform actual studies to optimize the process.

Implementation of a simple temperature controller in a CoolRunner™-II device.

This application note demonstrates how a CoolRunner™-II can be used as a power management device for multiple devices, including Virtex™-II and Spartan™-3.

This application note describes an implementation of a LIN controller on a Xilinx® CoolRunner™-II CPLD. A microcontroller interface is provided, but this could also be implemented as an IP core with minimal effort.

This document describes several different methods for interfacing 5V signals to CoolRunner™-II devices. These techniques may be used whenever voltage signal levels exceed the maximum input requirements of logic devices.

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

This application note contains a reference design consisting of HDL IP and Xilinx® Advanced Configuration Environment (ACE) software utilities that give designers great flexibility in creating in-system programming (ISP) solutions.

The flexibility of the CoolRunner™-II CPLD allows users to configure any I/O pin to act as a voltage reference (VREF) pin. This document describes the different methods and underlying rules for determining the number and placement of these VREF pins.

This application note describes the card-side implementation of an 16-bit CompactFlash (CF+)card interface using a CoolRunner™-II CPLD. Included in this implementation are the CIS, Attribute Memory Control and Status Registers, 16-bit Common Memory, and 8-bit I/O Interface. This design can be easily modified to interface to any memory, DSP or microcontroller.

This application note outlines the various ways designers can utilize the DataGATE feature of CoolRunner™-II CPLDs.

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family.

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power™ (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX).

This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD.

Frequently, the power voltage applied to a board is higher (or lower) than the nominal 1.8V VCCINT level required by CoolRunner™-II CPLDs. In these situations, power-ICs are commonly used to perform the required DC-to-DC conversion of the power voltage. These devices, known as regulators, take an unregulated input voltage and provide a regulated output voltage independent of input voltage variations or output current fluctuations. Many different types of regulators exist. This application note provides an explanation of each regulator type and presents some typical circuits to highlight currently available commercial regulators.

This application notes describes the CoolRunner™-II CPLD capability called “On the Fly”(OTF) Reconfiguration. OTF permits the CPLD to be operating with a design pattern and simultaneously acquire a second pattern during the operation of the first pattern. The second pattern can be configured into the device with a minimal disturbance to the operation of the device. Additional capabilities, applications and limits to this operation are discussed in further sections.

This application note describes the implementation of an 8-bit microcontroller design using a CoolRunner™-II CPLD. The PicoBlaze™ Microcontoller instructions can be customized to make an application-specific microcontroller. CoolRunner-II devices, the latest CPLD family from Xilinx® offers both low power and high-speed performance. A complete VHDL code for PicoBlaze microcontroller design and C code for its assembler are available with this application note.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™-II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master. To obtain the VHDL code described in this document, go to section VHDL Code Download and Disclaimer, page 19 for instructions. This design fits XC2C256 CoolRunner-II or XCR3256XL CoolRunner<™ XPLA3 CPLDs. For the CoolRunner-II CPLD version, please refer to XAPP348, CoolRunner™ Serial Peripheral Interface Master.

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner-II 256-macrocell CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 19 for instructions. This design fits both XPLA3 and CoolRunner-II CPLDs. For the CoolRunner XPLA3 CPLD version, please refer to XAPP333, CoolRunner CPLD I2C Bus Controller Implementation.

This document describes a reference design for interfacing CoolRunner™-II CPLDs with double data rate (DDR) SDRAM memory devices. The built reference design is capable of 100 MHz operation.

This application note describes the implementation of a single error correction, double error detection (SECDED) design with a CoolRunner™-II CPLD. CoolRunner-II devices are the latest CPLD from Xilinx® that offer both low power and high-speed performance. A complete VHDL design is available with this application note.

This document is designed to be a comprehensive description of the I/O structure of the CoolRunner™-II CPLD family. The I/O pins have the most dramatic externally observed behavior of any IC feature. This application note should help illustrate what the I/Os can and cannot do, as well as detail the limits of their drive and performance.

This document describes the demo board that uses the CoolRunner™-II 64-macrocell CPLD.

This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices.

This application note describes methods which will produce consistently fast designs when used with Xilinx® CoolRunner™-II CPLD family. More detail on this important new family of 1.8V CPLDs is available at the Xilinx Web site (www.xilinx.com), where the family and individual part data sheets can be found. Additional application literature is also available. Of particular interest is XAPP375, which discusses the timing of the CoolRunner-II CPLDs, and XAPP376, which discusses the basic operation of the macrocell and function block—the “logic engine” of the CoolRunner-II family.

This application note describes how to implement the CoolRunner™-II advanced features in the Xilinx software. These features include the DualEDGE triggered registers, clock divider, CoolCLOCK, DataGATE, Schmitt trigger inputs, and I/O termination types.

CoolRunner™-II RealDigital CPLDs are the only CPLDs to combine both high performance and low power to form the next generation CPLD. This application note describes the design methodologies that can be employed to obtain the lowest power possible using the CoolRunner-II CPLD by utilizing its unique power saving features.

CoolRunner™-II is the Xilinx® CPLD Family that raises the standard for Complex Programmable Logic Devices. CoolRunner-II delivers unmatched performance with the industry’s lowest power at highly competitive price points in an aggressive spectrum of packages. This application note details how CoolRunner-II CPLDs create logic within their CMOS fabric. In all likelihood, you will never need to know these details as the design software will automatically complete your design giving highest speed and lowest power with very little user direction. In the event that you would like to understand the inside details of how CoolRunner-II does its magic, this application note should help serve that need. For general CoolRunner-II information, also refer to the CoolRunner-II Family Data Sheet and individual device data sheets.

This document describes the CoolRunner™-II timing model. Understanding the CoolRunner-II timing model is essential to creating a CPLD design that meets the desired timing requirements.