XAPP944 - Using a Xilinx CoolRunner-II CPLD as a Data Stream Switch (PDF)
View Document Details
This application note shows how a Xilinx® CoolRunner™-II CPLD can be used as a simple logical switch that can quickly and reliably select between different MPEG video sources.
|
1.0 |
55 KB |
06/14/2006 |
XAPP940 - Using Xilinx CPLDs as Motor Controllers (PDF)
|
1.0 |
49 KB |
09/22/2006 |
XAPP914 - Connecting Intel PXA27x Processors to Hard-Disk Drives with a CoolRunner-II CPLD (PDF)
View Document Details
This application note shows how to connect an Intel Processor to a hard-disk drive. Was this document helpful? Yes | No
|
1.0 |
115 KB |
01/15/2006 |
XAPP910 - Doubling Counter/Timer Resolutions with CoolRunner-II (PDF)
View Document Details
This Application Note presents a method for doubling the frequency resolution of counter and timer applications using CoolRunner™-II. Was this document helpful? Yes | No
|
1.0 |
2.08 MB |
10/27/2005 |
XAPP906 - Supporting Multiple SD Devices with CoolRunner-II CPLDs (PDF)
|
1.1 |
340 KB |
09/14/2007 |
XAPP905 - Using CoolRunner-II with OMAP, XScale, i.MX & Other Chipsets (PDF)
|
1.0 |
48 KB |
08/25/2005 |
XAPP904 - CoolRunner-II Character LCD Module Interface (PDF)
|
1.0 |
949 KB |
08/22/2005 |
XAPP805 - Driving LEDs with Xilinx CPLDs (PDF)
|
1.0 |
254 KB |
04/08/2005 |
XAPP800 - Configuring Xilinx FPGAs with SPI Flash Memories Using CoolRunner-II CPLDs (PDF)
View Document Details
This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.
|
1.1.1 |
548 KB |
04/24/2008 |
XAPP799 - An SMBus/I2C-Compatible Port Expander (PDF)
View Document Details
This application note presents a design of a port expander that fits into a CoolRunner™-II XC2C32A device. The port expander is SMBus and I2C compatible.
|
1.1 |
2.34 MB |
08/02/2005 |
XAPP785 - Level Translation Using Xilinx CoolRunner-II CPLDs (PDF)
View Document Details
This application note demonstrates how to use a CoolRunner™-II CPLD as a Level Translator. Was this document helpful? Yes | No
|
1.0 |
78 KB |
06/22/2005 |
XAPP784 - Bulletproof CPLD Design Practices (PDF)
|
1.0 |
112 KB |
06/28/2005 |
XAPP693 - A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs (PDF)
View Document Details
This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.
|
1.1 |
100 KB |
01/19/2005 |
XAPP512 - Implementing Keypad Scanners with CoolRunner-II (PDF)
View Document Details
This application note provides a functional description of Verilog source code for a keypad scanner.
|
1.1 |
755 KB |
05/06/2005 |
XAPP501 - Configuration Quick Start Guidelines (PDF)
View Document Details
This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families. Was this document helpful? Yes | No
|
1.5 |
249 KB |
10/02/2007 |
XAPP444 - CPLD Fitting, Tips, and Tricks (PDF)
View Document Details
This application note helps guide designers in fitting designs into the smallest possible CPLD devices.
|
1.1 |
431 KB |
07/15/2005 |
XAPP440 - Power On Behavior of Xilinx CPLDs (PDF)
|
1.0 |
85 KB |
05/25/2006 |
XAPP439 - PCB Pad Pattern Design and Surface-Mount Considerations for QFN Packages (PDF)
View Document Details
This application note provides a good guideline on PCB pad pattern design and assembling of QFN packages for optimal reliability and quality. This is only a guideline, and users are encouraged to perform actual studies to optimize the process. Was this document helpful? Yes | No
|
1.0 |
123 KB |
04/11/2005 |
XAPP438 - CoolRunner-II Low Cost, Low Power Thermometer for Embedded Designs (PDF)
View Document Details
Implementation of a simple temperature controller in a CoolRunner™-II device. Was this document helpful? Yes | No
|
1.0 |
670 KB |
11/29/2004 |
XAPP436 - Managing Power with CoolRunner-II CPLDs (PDF)
View Document Details
This application note demonstrates how a CoolRunner™-II can be used as a power management device for multiple devices, including Virtex™-II and Spartan™-3. Was this document helpful? Yes | No
|
1.2 |
426 KB |
09/28/2005 |
XAPP432 - Implementing a LIN Controller on a CoolRunner-II CPLD (PDF)
View Document Details
This application note describes an implementation of a LIN controller on a Xilinx® CoolRunner™-II CPLD. A microcontroller interface is provided, but this could also be implemented as an IP core with minimal effort. Was this document helpful? Yes | No
|
1.1 |
456 KB |
04/03/2007 |
XAPP429 - 5V Tolerance Techniques for CoolRunner-II Devices (PDF)
View Document Details
This document describes several different methods for interfacing 5V signals to CoolRunner™-II devices. These techniques may be used whenever voltage signal levels exceed the maximum input requirements of logic devices. Was this document helpful? Yes | No
|
1.0 |
210 KB |
08/08/2003 |
XAPP427 - Implementation and Solder Reflow Guidelines for Pb-Free Packages (PDF)
View Document Details
This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages. Was this document helpful? Yes | No
|
2.2 |
157 KB |
01/30/2006 |
XAPP424 - Embedded JTAG ACE Player (PDF)
View Document Details
This application note contains a reference design consisting of HDL IP and Xilinx® Advanced Configuration Environment (ACE) software utilities that give designers great flexibility in creating in-system programming (ISP) solutions.
|
1.0.2 |
244 KB |
04/07/2008 |
XAPP399 - Assigning CoolRunner-II VREF Pins (PDF)
View Document Details
The flexibility of the CoolRunner™-II CPLD allows users to configure any I/O pin to act as a voltage reference (VREF) pin. This document describes the different methods and underlying rules for determining the number and placement of these VREF pins. Was this document helpful? Yes | No
|
1.1 |
147 KB |
07/25/2003 |
XAPP398 - CompactFlash Card Interface for CoolRunner-II CPLDs (PDF)
View Document Details
This application note describes the card-side implementation of an 16-bit CompactFlash (CF+)card interface using a CoolRunner™-II CPLD. Included in this implementation are the CIS, Attribute Memory Control and Status Registers, 16-bit Common Memory, and 8-bit I/O Interface. This design can be easily modified to interface to any memory, DSP or microcontroller. Was this document helpful? Yes | No
|
1.0 |
565 KB |
09/23/2003 |
XAPP395 - Using DataGATE in CoolRunner-II CPLDs (PDF)
View Document Details
This application note outlines the various ways designers can utilize the DataGATE feature of CoolRunner™-II CPLDs. Was this document helpful? Yes | No
|
1.2 |
471 KB |
09/22/2003 |
XAPP394 - Interfacing to Mobile SDRAM with CoolRunner-II CPLDs (PDF)
View Document Details
This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family. Was this document helpful? Yes | No
|
1.1 |
82 KB |
12/01/2003 |
XAPP393 - CoolRunner-II CPLD 8051 Microcontroller Interface (PDF)
View Document Details
This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers. Was this document helpful? Yes | No
|
1.0 |
108 KB |
01/15/2003 |
XAPP391 - Design of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD (PDF)
View Document Details
This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power™ (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX). Was this document helpful? Yes | No
|
1.0 |
343 KB |
01/15/2003 |
XAPP390 - Design of a Digital Camera with CoolRunner-II CPLDs (PDF)
View Document Details
This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD. Was this document helpful? Yes | No
|
1.1 |
1.68 MB |
09/27/2005 |
XAPP389 - Powering CoolRunner-II CPLDs (PDF)
View Document Details
Frequently, the power voltage applied to a board is higher (or lower) than the nominal 1.8V VCCINT level required by CoolRunner™-II CPLDs. In these situations, power-ICs are commonly used to perform the required DC-to-DC conversion of the power voltage. These devices, known as regulators, take an unregulated input voltage and provide a regulated output voltage independent of input voltage variations or output current fluctuations. Many different types of regulators exist. This application note provides an explanation of each regulator type and presents some typical circuits to highlight currently available commercial regulators. Was this document helpful? Yes | No
|
1.1 |
191 KB |
10/29/2007 |
XAPP388 - On the Fly Reconfiguration with CoolRunner-II CPLDs (PDF)
View Document Details
This application notes describes the CoolRunner™-II CPLD capability called “On the Fly”(OTF) Reconfiguration. OTF permits the CPLD to be operating with a design pattern and simultaneously acquire a second pattern during the operation of the first pattern. The second pattern can be configured into the device with a minimal disturbance to the operation of the device. Additional capabilities, applications and limits to this operation are discussed in further sections. Was this document helpful? Yes | No
|
1.2 |
223 KB |
05/15/2003 |
XAPP387 - PicoBlaze 8-Bit Microcontroller for CPLD Devices (PDF)
View Document Details
This application note describes the implementation of an 8-bit microcontroller design using a CoolRunner™-II CPLD. The PicoBlaze™ Microcontoller instructions can be customized to make an application-specific microcontroller. CoolRunner-II devices, the latest CPLD family from Xilinx® offers both low power and high-speed performance. A complete VHDL code for PicoBlaze microcontroller design and C code for its assembler are available with this application note. Was this document helpful? Yes | No
|
1.0 |
156 KB |
12/24/2002 |
XAPP386 - CoolRunner-II Serial Peripheral Interface Master (PDF)
View Document Details
This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™-II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master. To obtain the VHDL code described in this document, go to section VHDL Code Download and Disclaimer, page 19 for instructions. This design fits XC2C256 CoolRunner-II or XCR3256XL CoolRunner<™ XPLA3 CPLDs. For the CoolRunner-II CPLD version, please refer to XAPP348, CoolRunner™ Serial Peripheral Interface Master. Was this document helpful? Yes | No
|
1.0 |
159 KB |
12/24/2002 |
XAPP385 - CoolRunner-II CPLD I2C Bus Controller Implementation (PDF)
View Document Details
This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner-II 256-macrocell CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 19 for instructions. This design fits both XPLA3 and CoolRunner-II CPLDs. For the CoolRunner XPLA3 CPLD version, please refer to XAPP333, CoolRunner CPLD I2C Bus Controller Implementation. Was this document helpful? Yes | No
|
1.1 |
152 KB |
12/30/2003 |
XAPP384 - Interfacing to DDR SDRAM with CoolRunner-II CPLDs (PDF)
View Document Details
This document describes a reference design for interfacing CoolRunner™-II CPLDs with double data rate (DDR) SDRAM memory devices. The built reference design is capable of 100 MHz operation. Was this document helpful? Yes | No
|
1.0 |
482 KB |
02/14/2003 |
XAPP383 - Single Error Correction and Double Error Detection (SECDED) with CoolRunner-II CPLDs (PDF)
View Document Details
This application note describes the implementation of a single error correction, double error detection (SECDED) design with a CoolRunner™-II CPLD. CoolRunner-II devices are the latest CPLD from Xilinx® that offer both low power and high-speed performance. A complete VHDL design is available with this application note. Was this document helpful? Yes | No
|
1.0 |
60 KB |
09/26/2002 |
XAPP382 - CoolRunner-II I/O Characteristics (PDF)
View Document Details
This document is designed to be a comprehensive description of the I/O structure of the CoolRunner™-II CPLD family. The I/O pins have the most dramatic externally observed behavior of any IC feature. This application note should help illustrate what the I/Os can and cannot do, as well as detail the limits of their drive and performance. Was this document helpful? Yes | No
|
1.0 |
154 KB |
11/11/2002 |
XAPP381 - CoolRunner-II Demo Board (PDF)
View Document Details
This document describes the demo board that uses the CoolRunner™-II 64-macrocell CPLD. Was this document helpful? Yes | No
|
1.0 |
110 KB |
09/01/2002 |
XAPP380 - Building Crosspoint Switches with CoolRunner-II CPLDs (PDF)
View Document Details
This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices. Was this document helpful? Yes | No
|
1.0 |
80 KB |
06/05/2002 |
XAPP379 - High Speed Design with CoolRunner-II CPLDs (PDF)
View Document Details
This application note describes methods which will produce consistently fast designs when used with Xilinx® CoolRunner™-II CPLD family. More detail on this important new family of 1.8V CPLDs is available at the Xilinx Web site (www.xilinx.com), where the family and individual part data sheets can be found. Additional application literature is also available. Of particular interest is XAPP375, which discusses the timing of the CoolRunner-II CPLDs, and XAPP376, which discusses the basic operation of the macrocell and function block—the “logic engine” of the CoolRunner-II family. Was this document helpful? Yes | No
|
1.1 |
76 KB |
08/01/2002 |
XAPP378 - Using CoolRunner-II Advanced Features (PDF)
View Document Details
This application note describes how to implement the CoolRunner™-II advanced features in the Xilinx software. These features include the DualEDGE triggered registers, clock divider, CoolCLOCK, DataGATE, Schmitt trigger inputs, and I/O termination types. Was this document helpful? Yes | No
|
1.2 |
908 KB |
06/05/2005 |
XAPP377 - Low Power Design with CoolRunner-II CPLDs (PDF)
View Document Details
CoolRunner™-II RealDigital CPLDs are the only CPLDs to combine both high performance and low power to form the next generation CPLD. This application note describes the design methodologies that can be employed to obtain the lowest power possible using the CoolRunner-II CPLD by utilizing its unique power saving features. Was this document helpful? Yes | No
|
1.0 |
100 KB |
05/08/2002 |
XAPP376 - Understanding the CoolRunner-II Logic Engine (PDF)
View Document Details
CoolRunner™-II is the Xilinx® CPLD Family that raises the standard for Complex Programmable Logic Devices. CoolRunner-II delivers unmatched performance with the industry’s lowest power at highly competitive price points in an aggressive spectrum of packages. This application note details how CoolRunner-II CPLDs create logic within their CMOS fabric. In all likelihood, you will never need to know these details as the design software will automatically complete your design giving highest speed and lowest power with very little user direction. In the event that you would like to understand the inside details of how CoolRunner-II does its magic, this application note should help serve that need. For general CoolRunner-II information, also refer to the CoolRunner-II Family Data Sheet and individual device data sheets. Was this document helpful? Yes | No
|
1.0 |
105 KB |
01/03/2002 |
XAPP375 - Understanding the CoolRunner-II Timing Model (PDF)
View Document Details
This document describes the CoolRunner™-II timing model. Understanding the CoolRunner-II timing model is essential to creating a CPLD design that meets the desired timing requirements. Was this document helpful? Yes | No
|
1.5 |
133 KB |
02/28/2003 |
XAPP374 - CryptoBlaze: 8-Bit Security Microcontroller (PDF)
|