CoolRunner-II

Xilinx CoolRunner™-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3™ family in a single CPLD.

The CoolRunner™-II 32A-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 64A-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 128-macrocell device is designed for both high-performance and low-power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 384-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

The CoolRunner™-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.

This document describes the behavior of the I/Os under various operating conditions. It describes how to use the different termination modes, how to understand thresholds, and how loading affects the I/Os.

This document discusses thermal, electrical, moisture, and soldering characteristics of Xilinx® device packages.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

The purpose of this notice is to announce the addition of STATS ChipPAC in Singapore (SCS) as a qualified assembly partner for Plastic Quad Flat Pack (PQFP), Thin Quad Flat Pack (TQFP/VQFP), and Ball Grid Array in wire bond (BGA) packages.

Design File(s):

• Qualification Report for XCN06016

Notification of an error in some SVF files generated by certain versions of iMPACT that can result in improper programming of CoolRunner™-II CPLDs.

The XC2C32 and XC2C64 CPLD devices are being discontinued and will be replaced by enhanced devices in the CoolRunner™-II CPLD family.

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

This circuit revision increases the tolerance of the configuration circuitry to non-monotonic power supply ramps and provides a more robust solution in customer applications.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

Xilinx is discontinuing certain Spartan®, XC4000XL, CoolRunner™, and Programming Solution products.

To advice customers that Xilinx has added alternate shipping tray for 28mm x 28mm QFP packages and 31mm x 31mm BGA packages.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing certain Development Systems products.

To communicate that Xilinx is discontinuing certain Development Systems Products.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

This notification is to communicate that Xilinx is discontinuing certain Development Systems products.

To communicate that Xilinx is discontinuing certain Development Systems products

This application note shows how a Xilinx® CoolRunner™-II CPLD can be used as a simple logical switch that can quickly and reliably select between different MPEG video sources.

Design File(s):

• xapp944_source.zip.zip

This application note shows how to connect an Intel Processor to a hard-disk drive.

This Application Note presents a method for doubling the frequency resolution of counter and timer applications using CoolRunner™-II.

This appnote shows how to use a CoolRunner™-II to interface with multiple SD cards.

Design File(s):

• xapp906_design_files.zip

Using CoolRunner™-II CPLDs with standard chipsets.

Uses CoolRunner™-II to control dot matrix LCD module. Includes design file.

Design File(s):

• xapp904_code.zip

This application note describes how to drive LEDs using Xilinx CPLDs.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

Design File(s):

• xapp800.zip

This application note presents a design of a port expander that fits into a CoolRunner™-II XC2C32A device. The port expander is SMBus and I2C compatible.

Design File(s):

• XAPP799_designfiles.zip

This application note demonstrates how to use a CoolRunner™-II CPLD as a Level Translator.

Checklist application note giving best practice CPLD design methodology.

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

Design File(s):

• xapp693.zip
• xapp693.zip

This application note provides a functional description of Verilog source code for a keypad scanner.

Design File(s):

• xapp512__verilog.zip
• xapp512__verilog.zip

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

This application note helps guide designers in fitting designs into the smallest possible CPLD devices.

Design File(s):

• xapp444.zip
• xapp444.zip

Describes the bahavior of CPLDs during power up.

This application note provides a good guideline on PCB pad pattern design and assembling of QFN packages for optimal reliability and quality. This is only a guideline, and users are encouraged to perform actual studies to optimize the process.

Implementation of a simple temperature controller in a CoolRunner™-II device.

This application note demonstrates how a CoolRunner™-II can be used as a power management device for multiple devices, including Virtex®-II and Spartan®:-3.

This document describes several different methods for interfacing 5V signals to CoolRunner™-II devices. These techniques may be used whenever voltage signal levels exceed the maximum input requirements of logic devices.

This application note contains a reference design consisting of HDL IP and Xilinx® Advanced Configuration Environment (ACE) software utilities that give designers great flexibility in creating in-system programming (ISP) solutions.

Design File(s):

• xapp424.zip

The flexibility of the CoolRunner™-II CPLD allows users to configure any I/O pin to act as a voltage reference (VREF) pin. This document describes the different methods and underlying rules for determining the number and placement of these VREF pins.

This application note describes the card-side implementation of an 16-bit CompactFlash (CF+)card interface using a CoolRunner™-II CPLD. Included in this implementation are the CIS, Attribute Memory Control and Status Registers, 16-bit Common Memory, and 8-bit I/O Interface. This design can be easily modified to interface to any memory, DSP or microcontroller.

This application note outlines the various ways designers can utilize the DataGATE feature of CoolRunner™-II CPLDs.

This document describes the VHDL design for interfacing CoolRunner™-II CPLDs with low-power Mobile SDRAM memory devices. Mobile SDRAM is the ideal memory solution for wireless, handheld, and mobile computing applications, making this a perfect match with the Xilinx CoolRunner-II low-power CPLD family.

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™-II CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power™ (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX).

This application note describes a digital camera reference design that uses a CoolRunner-II™ CPLD.

Frequently, the power voltage applied to a board is higher (or lower) than the nominal 1.8V VCCINT level required by CoolRunner™-II CPLDs. In these situations, power-ICs are commonly used to perform the required DC-to-DC conversion of the power voltage. These devices, known as regulators, take an unregulated input voltage and provide a regulated output voltage independent of input voltage variations or output current fluctuations. Many different types of regulators exist. This application note provides an explanation of each regulator type and presents some typical circuits to highlight currently available commercial regulators.

This application notes describes the CoolRunner™-II CPLD capability called “On the Fly”(OTF) Reconfiguration. OTF permits the CPLD to be operating with a design pattern and simultaneously acquire a second pattern during the operation of the first pattern. The second pattern can be configured into the device with a minimal disturbance to the operation of the device. Additional capabilities, applications and limits to this operation are discussed in further sections.

This application note describes the implementation of an 8-bit microcontroller design using a CoolRunner™-II CPLD. The PicoBlaze™ Microcontoller instructions can be customized to make an application-specific microcontroller. CoolRunner-II devices, the latest CPLD family from Xilinx® offers both low power and high-speed performance. A complete VHDL code for PicoBlaze microcontroller design and C code for its assembler are available with this application note.

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner-II 256-macrocell CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller. To obtain the VHDL code described in this document, go to section VHDL Code Download, page 19 for instructions. This design fits both XPLA3 and CoolRunner-II CPLDs. For the CoolRunner XPLA3 CPLD version, please refer to XAPP333, CoolRunner CPLD I2C Bus Controller Implementation.

This document describes a reference design for interfacing CoolRunner™-II CPLDs with double data rate (DDR) SDRAM memory devices. The built reference design is capable of 100 MHz operation.

This application note describes the implementation of a single error correction, double error detection (SECDED) design with a CoolRunner™-II CPLD. CoolRunner-II devices are the latest CPLD from Xilinx® that offer both low power and high-speed performance. A complete VHDL design is available with this application note.

This document is designed to be a comprehensive description of the I/O structure of the CoolRunner™-II CPLD family. The I/O pins have the most dramatic externally observed behavior of any IC feature. This application note should help illustrate what the I/Os can and cannot do, as well as detail the limits of their drive and performance.

This document describes the demo board that uses the CoolRunner™-II 64-macrocell CPLD.

This application note provides a functional description of VHDL source code for a N x N Digital Crosspoint Switch. The code is designed with eight inputs and eight outputs in order to target the 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higher density devices.

This application note describes methods which will produce consistently fast designs when used with Xilinx® CoolRunner™-II CPLD family. More detail on this important new family of 1.8V CPLDs is available at the Xilinx Web site (www.xilinx.com), where the family and individual part data sheets can be found. Additional application literature is also available. Of particular interest is XAPP375, which discusses the timing of the CoolRunner-II CPLDs, and XAPP376, which discusses the basic operation of the macrocell and function block—the “logic engine” of the CoolRunner-II family.

This application note describes how to implement the CoolRunner™-II advanced features in the Xilinx software. These features include the DualEDGE triggered registers, clock divider, CoolCLOCK, DataGATE, Schmitt trigger inputs, and I/O termination types.

CoolRunner™-II RealDigital CPLDs are the only CPLDs to combine both high performance and low power to form the next generation CPLD. This application note describes the design methodologies that can be employed to obtain the lowest power possible using the CoolRunner-II CPLD by utilizing its unique power saving features.

CoolRunner™-II is the Xilinx® CPLD Family that raises the standard for Complex Programmable Logic Devices. CoolRunner-II delivers unmatched performance with the industry’s lowest power at highly competitive price points in an aggressive spectrum of packages. This application note details how CoolRunner-II CPLDs create logic within their CMOS fabric. In all likelihood, you will never need to know these details as the design software will automatically complete your design giving highest speed and lowest power with very little user direction. In the event that you would like to understand the inside details of how CoolRunner-II does its magic, this application note should help serve that need. For general CoolRunner-II information, also refer to the CoolRunner-II Family Data Sheet and individual device data sheets.

This document describes the CoolRunner™-II timing model. Understanding the CoolRunner-II timing model is essential to creating a CPLD design that meets the desired timing requirements.

This application note provides a basic outline for creating a cryptographic processor using CoolRunner™-II devices and a CPLD version of the PicoBlaze™ processor.

This application note describes the implementation of a Smart Card Reader design with a CoolRunner™-II CPLD. Different from most of the software-based smart card reader computer systems, this CoolRunner-II CPLD implementation is a hardware solution. There is no software development needed in this design. This application note explains the low-level protocol of the Smart Card Reader and its hardware implementation.

This application note outlines three Galois multiplier solutions of increasing bit-length and complexity, stepping through generation and verification processes.

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for controlling a serial ADC in a portable handheld application. This document provides an explanation of the VHDL code for the CoolRunner CPLD.

This application note describes the use of a Xilinx CoolRunner™ XPLA3 CPLD to implement a NAND Flash memory interface. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for memory interface applications.

This document details the VHDL implementation of an system Management Bus (SMBus) controller in a Xilinx CoolRunner™ XPLA3 256-macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SMBus controller.

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.

This application note describes system design techniques using a low power CoolRunner™ CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to offload operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings.

This document details specific implementation techniques which may be used to decrease power consumption in CPLD designs.

This application note illustrates the implementation of an IrDA and UART system using a CoolRunner™ XPLA3 CPLD. The note also describes the fundamental building blocks required to create a half-duplex IrDA and full-duplex UART interface design.

This document provides a brief description of how to perform ISP operations with XPLA3 CPLDs.

This document describes the features and benefits of the I/O cells provided by Xilinx® CoolRunner™ XPLA3 CPLDs.

This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. This note also discusses the functionality of the UART.

This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder and discusses the reasons to use Manchester code. The code can be compiled into either the Xilinx XC9572 or XCR3064XL CPLD.

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™ CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX ).

This document provides a description of the CMOS output structures of the CoolRunner™ CPLDs and details some advantages of using true CMOS (rail-to-rail capable) output drivers.

This application note provides a quick and simple method for estimating power consumption of CoolRunner-II CPLDs. As an alternative to XPower, power can be quickly and easily computed using the provided equation and coefficients as described in this application note.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note documents using a Xilinx® CPLD as a motor controller.

Design File(s):

• xapp940.zip

This application note describes an implementation of a LIN controller on a Xilinx® CoolRunner™-II CPLD. A microcontroller interface is provided, but this could also be implemented as an IP core with minimal effort.

Design File(s):

• xapp432_lin_controller.zip
• xapp432_lin_io_module.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™-II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master. To obtain the VHDL code described in this document, go to section VHDL Code Download and Disclaimer, page 19 for instructions. This design fits XC2C256 CoolRunner-II or XCR3256XL CoolRunner XPLA3 CPLDs. For the CoolRunner-II CPLD version, refer to XAPP348, CoolRunner Serial Peripheral Interface Master.

Design File(s):

• xapp386.zip

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

Design File(s):

• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

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• IPC-1752 Form

100% Material Data Declaration Sheet (Pb-free PLCC)

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ100 package

Design File(s):

• IPC-1752 Form

VQG44 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

VQG100 - Material Declaration Data Sheet (Pb-free VQFP)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for VQ44 package

Design File(s):

• IPC-1752 Form

An overview of CoolRunner™-II CPLD applications in the Digital Video Applications market.

This White Paper discusses the advantages of using DataGATE (input gating) over sleep modes.

This White Paper describes CoolRunner™-II characteristics when powered by non-standard I/O voltages.

This document demonstates the dramatic power savings that are obtained using the DataGATE feature.

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.

White Paper on the advantages and cost savings of using Xilinx CPLDs instead of 7400 Discrete Devices.

Cell phone handsets (or “terminals,” as they’re called in Europe) are among the most dynamic products in the electronics market today. From their original analog roots, they have evolved into nearly pure digital devices with as much functionality as complex PDAs. Consumers who once evaluated handsets based on their ability to make high-quality local calls now take call clarity as a given. Their choices instead rest on characteristics ranging from a handset’s "skin" color to its ability to support streaming video. Buyers, even those shopping for low-cost handsets, increasingly demand these kinds of features: "extras" are well on their way to becoming standards. This shift puts manufacturers in a bind as they try to balance low cost with the ever-increasing consumer insistence on new features. Should customers pay for these features outright, or should their monthly payments subsidize the handset cost?

It doesn’t usually take very long to create an FPGA design. Recently, however, a Xilinx competitor ran an ad declaring that while an FPGA can take up to a year to design, it can be cloned in only a second. Are FPGA designs really that insecure? While the ad seems absurdly hyperbolic, it is true that the bitstreams of some volatile FPGAs can be cloned. While it’s unlikely that cloning could happen in "a second," fears about the insecurity of design efforts are valid ones. To alleviate these anxieties, this white paper will show you how to substantially secure the bitstream and the overall design of FPGAs using Xilinx CoolRunner™-II CPLDs.

This white paper discusses the FPD market and looks in closer detail at Plasma Display Panels and Liquid Crystal Displays in particular. An overview of where Xilinx devices fit in digital video systems is followed by a market overview of the flat panel display industry. The value proposition for Xilinx devices is presented, followed by a detailed discussion of the relationship of product features and resources to FPD system requirements.

This White Paper discusses applications for CoolRunner™-II CPLDs in POS and HPOS terminals.

This White Paper shows how the low power CoolRunner™-II CPLD can be used to incorporate new functionality into a portable educational toy quickly, cost effectively, and with very little additional power consumption.

This white paper discusses the use of CoolRunner™-II CPLDs in portable navigation devices.

Reference Manual for CoolRunner™-II Evaluation Board

Tutorial for CoolRunner™-II Evaluation Board.