CoolRunner XPLA3

This application note describes how to drive LEDs using Xilinx CPLDs.

Checklist application note giving best practice CPLD design methodology.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Describes the bahavior of CPLDs during power up.

This document focuses on the design of a wireless transceiver using CoolRunner™ CPLDs. The wireless transceiver is implemented using the CoolRunner demo board. The wireless transceiver is the perfect application of the low-power capabilities of a CoolRunner CPLD.

This document describes the design implementation for controlling a Texas Instruments ADS7870 Analog to Digital Converter (ADC) in a Xilinx CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for controlling a serial ADC in a portable handheld application. This document provides an explanation of the VHDL code for the CoolRunner CPLD.

This application note describes the use of a Xilinx CoolRunner™ XPLA3 CPLD to implement a NAND Flash memory interface. CoolRunner CPLDs are the lowest power CPLD available and the ideal target device for memory interface applications.

This document details the VHDL implementation of an system Management Bus (SMBus) controller in a Xilinx CoolRunner™ XPLA3 256-macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SMBus controller.

This application note provides an introduction to the capabilities and functionality of the User Constraint File (UCF) for CoolRunner™ XPLA3 CPLD designs in WebPACK™ Project Navigator.

This document details the VHDL implementation of an 8051 microcontroller interface in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making these CPLDs the perfect interface devices for many of today’s popular microcontrollers.

This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ XPLA3 CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.

This application note describes system design techniques using a low power CoolRunner™ CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to offload operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings.

This document details specific implementation techniques which may be used to decrease power consumption in CPLD designs.

This application note illustrates the implementation of an IrDA and UART system using a CoolRunner™ XPLA3 CPLD. The note also describes the fundamental building blocks required to create a half-duplex IrDA and full-duplex UART interface design.

This document provides a brief description of how to perform ISP operations with XPLA3 CPLDs.

This document describes the features and benefits of the I/O cells provided by Xilinx CoolRunner™ XPLA3 CPLDs.

This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. This note also discusses the functionality of the UART.

This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder and discusses the reasons to use Manchester code. The code can be compiled into either the Xilinx XC9572 or XCR3064XL CPLD.

This document details the VHDL implementation of a fibre channel byte-oriented transmission encoder and decoder in a Xilinx® CoolRunner™ CPLD. CoolRunner CPLDs are the lowest power CPLDs available today and can be utilized in any network design where reliable point-to-point transceivers are required. CoolRunner CPLDs utilize the patented Fast Zero Power (FZP) design technique to simultaneously deliver high performance and low power consumption. These devices offer pin-to-pin delays of 5.0 ns, and less than 100 µA of standby current (approximately 1/3 of the power consumed by other competing CPLDs at fMAX ).

This document describes the macrocell configurations of Xilinx® CoolRunner™ XPLA CPLDs.

This document highlights the advantages of utilizing the universal control terms provided in the CoolRunner™ XPLA3 CPLD architecture. This application note also discusses design examples showing the efficiency of these universal control terms.

This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller.

This document highlights the architectural features provided with CoolRunner™ CPLDs that enable pin assignments to be maintained through many design iterations.

This document provides a description of the CMOS output structures of the CoolRunner™ CPLDs and details some advantages of using true CMOS (rail-to-rail capable) output drivers.

MP3 portable players are the trend in music-listening technology. These players do not include any mechanical movements, thereby making them ideal for listening to music during any type of activity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music in a lot less space than current CD technology. Software is readily available to create MP3 files from an existing CD, and the user can then download these files into a portable MP3 player to be enjoyed in almost any environment.

This application note provides a quick and simple method for estimating power consumption of CoolRunner™ XPLA3 CPLDs. As an alternative to XPower, power can be quickly and easily computed using the equation and coefficients provided in this application note.

This document highlights the few major differences between ABEL and PHDL. All other PHDL constructs and syntax not discussed in this document are supported in ABEL. Most PHDL designs will be accepted in Xilinx Project Navigator with just a modification to the file extension.

The purpose of this application note is to investigate the PCI (Peripheral Component Interface) environment when using 5 volt tolerant, 3.3 volt supply integrated circuits. In particular, we will examine the meaning of the statement "PCI compliant" when used in CPLD or FPGA data sheets.

This application note describes power-up characteristics for CoolRunner™ CPLDs that may be of interest, depending upon where and how the devices are used.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.