ISE 11

Installation, licensing, and release information for ISE® Design Suite 11

This Answer Record describes the Known Issues for the Spartan-6 FPGA generation used with the ISE Design Suite 11.

The ISE Design Suite 12.1 Release Notes and Licensing Guide found on xilinx.com contains installation instructions, system requirements, and other general information.  This Known Issues Answer Record is a supplement to the release notes documentation and contains links to information on known issues in the design tools that might be resolved in future versions.

NOTE: For IP Known Issues, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

The ISE® 11.x, 12.x and 13.1 TRCE/Timing Analyzer tools do not correctly analyze certain control signals and address lines of the Virtex®-6 36Kb BRAM (RAMB36E1), 18Kb BRAM (RAMB18E1), and 18Kb FIFO (FIFO18E1) when used in SDP, TDP, or ECC modes, potentially resulting in unreported setup and hold time violations. The unreported violations can result in read and write errors in silicon and are not reported in the unconstrained path report section of the timing report.

Are there any Virtex-6 FPGA related known issues with the 11.2, 11.3, 11.4, or 11.5 ISE Design Suite software release?

 * Please note the Virtex-6 FPGA Production designs must use 12.1 or later ISE software. See (Xilinx Answer 35493) for Virtex-6 FPGA related software known issues for 12.x ISE Design Suite.

Licensing, Download & Installation FAQs

This Answer Record is a supplement to the Release Notes and Installation Guide and contains links to Answer Records that contain information on known issues in the ISE® Design Suite.

This Known Issues Answer Record is a supplement to the 11.2 Release Notes and contains links to information on known issues in the iMPACT configuration tool that might be resolved in future versions.

To inform you of changes in relation to part numbers used to order Xilinx® ISE® Design Suite software and fee-based LogiCORE™ IP cores.

To communicate that Xilinx will not be enhancing the AccelDSP™ synthesis tool and starting with ISE® Design Suite 12.1 will be discontinuing the AccelDSP synthesis tool as part of the DSP Edition and System Edition of ISE Design Suite

A quick introduction to SmartXplorer and how its capabilities can be used to help achieve timing closure.

Design File(s):

• SmartXplorer Tutorial Examples

A quick introduction to SmartXplorer and how its capabilities can be used to help achieve timing closure.

Design File(s):

• SmartXplorer Tutorial Examples

This tutorial provides a quick introduction to the main Schematic Viewer capabilities and how they can be used for design analysis and debugging.

This one page document contains a link to the ISE® Quick Start video tutorial.

This tutorial gives a description of the features and additions to Xilinx® ISE™ 11. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools.

Design File(s):

• Watch EDIF Design Files
• Watch Schematic Design Files
• Watch Verilog Design Files
• Watch VHDL Design Files

This tutorial provides advice on how to use the Xilinx® Power Tools for accurate power consumption estimation. The tutorial focuses on a simple Virtex®-6 and Spartan®-6 design for use in both an XPower Estimator (XPE) spreadsheet and XPower Analyzer (XPA) to illustrate Power Tool usage on the designs. This tutorial also describes the power optimization options in the ISE implementations tools.

Design File(s):

• ug733.zip

The ISE® (ISim) In-Depth Tutorial provides Xilinx PLD designers with a detailed introduction of the ISE Simulator (ISim) software. After you have completed the tutorial, you will have a thorough understanding of how to analyze and debug your design via HDL simulation.

Design File(s):

• ug682.zip

This is the collection of manuals for the 11.x ISE® software release. It includes all books and help for the 11.x release, with updates created for the 11.2, and 11.3, and 11.4 update releases.

This book describes the command line programs for the Xilinx® development system. Formerly known as the Development System Reference Guide, the User Guide had a name refresh and is now the Command Line Tools User Guide.

The Xilinx® Constraints Guide describes constraints and attributes that can be attached to designs for Xilinx FPGA and CPLD devices.

Designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs).

Describes the XST synthesis tool, including instructions for running and controlling XST, discusses coding techniques for designing circuits using HDL, and gives guidelines to leverage built-in FPGA optimization techniques for Virtex®-6 and Spartan®-6.

This manual describes timing closure in high-performance Xilinx® FPGA designs.

This help system provides information about how to use the Xilinx® Integrated Software Environment.

This document describes the Xilinx® ISim Hardware Description Language (HDL) simulator that enables you to perform functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs.

This document describes Xilinx® Synthesis Technology (XST) support for Hardware Description Language (HDL), Xilinx devices, and design constraints for the Xilinx ISE® Design Suite software

Glossary for ISE Design Suite documentation

This document describes how the Data2MEM software tool automates and simplifies setting the contents of Block RAM memory on Xilinx® FPGA family products.

Discusses processes and mechanisms available in the ISE® Design Suite and various Cadence tools to efficiently implement an FPGA on a PCB.

Discusses processes and mechanisms available in the ISE® Design Suite and various Mentor Graphics tools to efficiently implement an FPGA on a PCB.

Describes circuit design elements associated with the Virtex®-6 architecture. Details for each element include VHDL and Verilog instantiation code, schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Spartan®-6 architecture. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Virtex®-6 architecture. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Spartan®-6 architecture. Details for each element include VHDL and Verilog instantiation code, schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Virtex®-5 architecture. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Virtex®-4 architecture. Details for each element include VHDL and Verilog instantiation code, schematic symbols, truth tables, and other information specific to the design element.

This guide describes circuit design elements associated with the Virtex® -5 architecture. Details for each element include VHDL and Verilog instantiation code, schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Virtex®-4 architecture. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

This version of the Libraries Guide describes the primitives that comprise the Xilinx Unified Libraries for the Spartan®:-3A and Spartan-3A DSP architectures, and includes examples of instantiation code for each element.

Describes circuit design elements associated with the Spartan® -3A and Spartan® -3A DSP architectures. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

This version of the Libraries Guide describes the primitives that comprise the Xilinx Unified Libraries for the Spartan®-3 architecture, and includes examples of instantiation code for each element.

This version of the Libraries Guide describes the primitives and macros that comprise the Xilinx Unified Libraries for the Spartan®-3 architecture, and includes examples of instantiation code for each element

Describes circuit design elements associated with the Spartan®-3E architecture. Details for each element include VHDL and Verilog instantiation code, schematic symbols, truth tables, and other information specific to the design element.

Describes circuit design elements associated with the Spartan® -3E architecture. Details for each element include schematic symbols, truth tables, and other information specific to the design element.

This version of the Libraries Guide describes design elements available for CPLD architectures.